公开(公告)号：WO2018182700A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025447

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： RACHMADY, Willy ,  MA, Sean T. ,  METZ, Matthew V. ,  MINUTILLO, Nicholas G. ,  HUANG, Cheng-Ying ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S. ,  GHANI, Tahir

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66

Abstract: Solid-state assemblies including dielectric lining layers having localized charges are provided. Processes to form the solid-state assemblies also are provided. The solid-state assemblies can included in CMOS transistors, where first dielectric lining layers having localized charges of positive polarity can be adjacent to the PMOS member and a second dielectric lining layers having localized charges of positive polarity can be adjacent to an NMOS member. The first dielectric lining layers can be adjacent to a first gate electrode of the CMOS transistor, and the second dielectric lining can be adjacent to a second gate electrode of the CMOS transistor. The first dielectric lining layers and the second dielectric lining layers can improve, at least in part, the performance of the CMOS transistor by attracting mobile carriers into respective transport channels of the PMOS member and the NMOS member.

公开(公告)号：WO2019132891A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/068563

申请日：2017-12-27

Applicant: INTEL CORPORATION

Inventor： DEWEY, Gilbert ,  MA, Sean T. ,  GHANI, Tahir ,  RACHMADY, Willy ,  HUANG, Cheng-Ying ,  MURTHY, Anand S. ,  KENNEL, Harold W. ,  MINUTILLO, Nicholas G. ,  METZ, Matthew V.

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

Abstract: Transistors having a plurality of channel semiconductor structures, such as fins, over a dielectric material. A source and drain are coupled to opposite ends of the structures and a gate stack intersects the plurality of structures between the source and drain. Lateral epitaxial overgrowth (LEO) may be employed to form a super-lattice of a desired periodicity from a sidewall of a fin template structure that is within a trench and extends from the dielectric material. Following LEO, the super-lattice structure may be planarized with surrounding dielectric material to expose a top of the super-lattice layers. Alternating ones of the super-lattice layers may then be selectively etched away, with the retained layers of the super-lattice then laterally separated from each other by a distance that is a function of the super-lattice periodicity. A gate dielectric and a gate electrode may be formed over the retained super-lattice layers for a channel of a transistor.

公开(公告)号：WO2018063403A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/055028

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： DEWEY, Gilbert ,  METZ, Matthew V. ,  MA, Sean T. ,  HUANG, Cheng-Ying ,  GHANI, Tahir ,  MURTHY, Anand S. ,  KENNEL, Harold W. ,  MINUTILLO, Nicholas G. ,  KAVALIEROS, Jack T. ,  RACHMADY, Willy

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.

Abstract translation: 一种晶体管器件，包括设置在源极和漏极之间的衬底上的沟道，设置在所述沟道上的栅电极，其中所述沟道包括沟道材料，所述沟道材料与相同材料的本体分离 在衬底上。 一种方法，包括在集成电路衬底上的电介质层中形成沟槽，所述沟槽包括用于包括宽度的晶体管主体的尺寸; 在沟槽的一部分中沉积间隔层，间隔层使沟槽的宽度变窄; 穿过间隔层在沟槽中形成沟道材料; 使所述介电层凹陷以限定所述沟道材料的第一部分和所述沟道材料的第二部分; 以及将沟道材料的第一部分与沟道材料的第二部分分开。

公开(公告)号：WO2019066880A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054193

申请日：2017-09-28

Applicant: INTEL CORPORATION ,  MA, Sean T. ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  KENNEL, Harold W. ,  HUANG, Cheng-Ying ,  METZ, Matthew V. ,  MINUTILLO, Nicholas G. ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S.

Inventor： MA, Sean T. ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  KENNEL, Harold W. ,  HUANG, Cheng-Ying ,  METZ, Matthew V. ,  MINUTILLO, Nicholas G. ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S.

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: Group III-V semiconductor devices having asymmetric source and drain structures and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. The drain structure has a wider band gap than the source structure. A gate structure is over the channel structure.

公开(公告)号：WO2018125081A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/068885

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： RACHMADY, Willy ,  MURTHY, Anand S. ,  METZ, Matthew V. ,  MINUTILLO, Nicholas G. ,  MA, Sean T. ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  GHANI, Tahir

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/73 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/778 ,  H01L29/785

Abstract: Techniques are disclosed for forming transistors employing a blanket-grown metamorphic buffer layer. As can be understood based on this disclosure, employing the buffer layer enables the integration of relatively high-quality (or device-quality) epitaxial semiconductor material with a substrate that it could not otherwise be integrated with due to a lattice mismatch. To provide an example, the techniques can enable the monolithic formation of relatively high-quality InGaAs for highly scaled InGaAs transistors above a Si substrate by employing an intervening InAlAs metamorphic buffer layer. Note that metamorphic designates that the layer has been grown beyond its strain relaxation critical thickness. Achieving a metamorphic thickness for the buffer layer allows the lattice mismatch that would otherwise be present between the epitaxial semiconductor material and the substrate material to be mitigated. In some cases, the buffer layer also provides electrical isolation for the overlying epitaxial semiconductor material.