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    VERTICAL DIODE IN STACKED TRANSISTOR ARCHITECTURE
    1.
    发明申请
    VERTICAL DIODE IN STACKED TRANSISTOR ARCHITECTURE 审中-公开

    公开(公告)号：WO2019143340A1

    公开(公告)日：2019-07-25

    申请号：PCT/US2018/014267

    申请日：2018-01-18

    Applicant: INTEL CORPORATION

    Inventor： LILAK, Aaron D. ,  MORROW, Patrick ,  PHAN, Anh ,  HUANG, Cheng-Ying ,  MEHANDRU, Rishabh ,  DEWEY, Gilbert ,  RACHMADY, Willy

    IPC: H01L27/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/861 ,  H01L21/8234 ,  H01L27/092

    Abstract: An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

    DIELECTRIC LINING LAYERS FOR SEMICONDUCTOR DEVICES
    3.
    发明申请
    DIELECTRIC LINING LAYERS FOR SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：WO2018182700A1

    公开(公告)日：2018-10-04

    申请号：PCT/US2017/025447

    申请日：2017-03-31

    Applicant: INTEL CORPORATION

    Inventor： RACHMADY, Willy ,  MA, Sean T. ,  METZ, Matthew V. ,  MINUTILLO, Nicholas G. ,  HUANG, Cheng-Ying ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S. ,  GHANI, Tahir

    IPC: H01L29/49 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66

    Abstract: Solid-state assemblies including dielectric lining layers having localized charges are provided. Processes to form the solid-state assemblies also are provided. The solid-state assemblies can included in CMOS transistors, where first dielectric lining layers having localized charges of positive polarity can be adjacent to the PMOS member and a second dielectric lining layers having localized charges of positive polarity can be adjacent to an NMOS member. The first dielectric lining layers can be adjacent to a first gate electrode of the CMOS transistor, and the second dielectric lining can be adjacent to a second gate electrode of the CMOS transistor. The first dielectric lining layers and the second dielectric lining layers can improve, at least in part, the performance of the CMOS transistor by attracting mobile carriers into respective transport channels of the PMOS member and the NMOS member.

    VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS
    4.
    发明申请
    VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS 审中-公开

    公开(公告)号：WO2019168519A1

    公开(公告)日：2019-09-06

    申请号：PCT/US2018/020188

    申请日：2018-02-28

    Applicant: INTEL CORPORATION

    Inventor： HUANG, Cheng-Ying ,  KAVALIEROS, Jack ,  YOUNG, Ian ,  METZ, Matthew ,  RACHMADY, Willy ,  AVCI, Uygar ,  AGRAWAL, Ashish ,  CHU-KUNG, Benjamin

    IPC: H01L29/73 ,  H01L29/732 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/10

    Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of later TFETs. In an embodiment, the disclosed vertical TFET can have a channel that includes the functionality of a drain. In an embodiment, the channel can be unintentionally doped (UID).

    REDUCED TRANSISTOR RESISTANCE USING DOPED LAYER
    7.
    发明申请
    REDUCED TRANSISTOR RESISTANCE USING DOPED LAYER 审中-公开
    使用掺杂层降低晶体管电阻

    公开(公告)号：WO2018063363A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2016/054889

    申请日：2016-09-30

    Applicant: INTEL CORPORATION

    Inventor： HUANG, Cheng-Ying ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  KAVALIEROS, Jack T. ,  MA, Sean T.

    IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66

    Abstract: An embodiment includes a transistor comprising: first, second, and third layers each including a group III-V material; a channel included in the second layer, which is between the first and third layers; and a gate having first and second gate portions; wherein (a)(i) the first and third layers are doped, (a)(ii) the channel is between the first and second gate portions and the second gate portion is between the channel and a substrate, (a)(iii) a first axis intersects the first, second, and third layers but not the first gate portion, and (a)(iv) a second axis, parallel to the first axis, intersects the first and second gate portions and the channel. Other embodiments are described herein.

    Abstract translation: 一个实施例包括晶体管，该晶体管包括：第一层，第二层和第三层，各自包括III-V族材料; 包括在第一层和第三层之间的第二层中的通道; 以及具有第一和第二门部分的门; （a）（i）掺杂第一和第三层，（a）（ii）沟道位于第一和第二栅极部分之间，第二栅极部分位于沟道和衬底之间，（a）（iii） 第一轴与第一层，第二层和第三层相交，但不与第一门部相交，以及（a）（iv）平行于第一轴的第二轴与第一和第二门部以及通道相交。 这里描述了其他实施例。

    SYSTEMS, METHODS AND DEVICES FOR ISOLATION FOR SUBFIN LEAKAGE
    8.
    发明申请
    SYSTEMS, METHODS AND DEVICES FOR ISOLATION FOR SUBFIN LEAKAGE 审中-公开
    系统，方法和装置隔离SUBFIN泄漏

    公开(公告)号：WO2018063194A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2016/054196

    申请日：2016-09-28

    Applicant: INTEL CORPORATION

    Inventor： CHU-KUNG, Benjamin ,  LE, Van ,  SUNG, Seung Hoon ,  KAVALIEROS, Jack ,  AGRAWAL, Ashish ,  KENNEL, Harold ,  CHOUKSEY, Siddharth ,  MURTHY, Anand ,  GHANI, Tahir ,  GLASS, Glenn ,  HUANG, Cheng-Ying

    IPC: H01L29/10 ,  H01L29/66

    Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.

    Abstract translation: 通过晕环注入可以减轻关于硅锗（SiGe）/浅沟槽隔离（STI）界面的子鳍泄漏问题。 晕环注入用于形成高电阻层。 例如，硅衬底层204耦合到SiGe层，SiGe层耦合到锗（Ge）层。 栅层设置在Ge层上。 在Ge层中注入植入物，导致该层变得更加电阻。 但是，由于受到门的保护（或覆盖），某个区域不会接收到植入物。 该区域比Ge层的其余部分保持较低的电阻。 在一些实施例中，可以蚀刻Ge层的电阻区域和/或可以执行底切（蚀刻底切或EUC）以暴露Ge层的未注入Ge区域。

    SWITCHING DEVICE HAVING GATE STACK WITH LOW OXIDE GROWTH
    10.
    发明申请
    SWITCHING DEVICE HAVING GATE STACK WITH LOW OXIDE GROWTH 审中-公开

    公开(公告)号：WO2020081040A2

    公开(公告)日：2020-04-23

    申请号：PCT/US2017/068390

    申请日：2017-12-26

    Applicant: INTEL CORPORATION

    Inventor： RACHMADY, Willy ,  HUANG, Cheng-Ying ,  DEWEY, Gilbert

    IPC: H01L29/49

    Abstract: An embodiment includes a system comprising: a switching device that includes a fin; and a source contact on a source, a gate contact on a channel, and a drain contact on a drain; wherein the gate contact includes: (a)(i) a first layer that includes oxygen, the first layer directly contacting the fin, (a)(ii) a second layer that includes a dielectric material, (c) a third layer that includes at least one of aluminum, titanium, ruthenium, zirconium, hafnium, tantalum, niobium, vanadium, thorium, barium, magnesium, cerium, and lanthanum, and (a)(iii) a fourth layer that includes a metal, wherein (b)(i) the source contact, the gate contact, and the drain contact are all on the fin, and (b)(ii) the second layer is between the first and fourth layers. Other embodiments are described herein.

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