公开(公告)号：WO2016018542A1

公开(公告)日：2016-02-04

申请号：PCT/US2015/037735

申请日：2015-06-25

Applicant: INTEL IP CORPORATION

Inventor： BURBIDGE, Richard ,  MARTINEZ TARRADELL, Marta ,  HEO, Youn Hyoung

IPC: H04W48/02 ,  H04W48/08 ,  H04W48/20

CPC classification number: H04W48/04 ,  H04W48/02 ,  H04W48/20

Abstract: A user equipment having varied cell barring times is disclosed. The system includes circuitry and a control unit. The circuitry is configured to attempt cell selection of a cell and obtain barring information associated with the cell upon the cell being barred. The control unit is configured to initial selection of the cell and to determine a varied barring time at least partially based on the barring information and system characteristics upon the cell being barred.

Abstract translation: 公开了具有不同细胞封隔时间的用户设备。 该系统包括电路和控制单元。 电路被配置为尝试在小区被禁止时对小区进行小区选择并获得与小区相关联的限制信息。 所述控制单元被配置为初始选择所述单元并且至少部分地基于所述单元被禁止的禁止信息和系统特性来确定变化的限制时间。

公开(公告)号：WO2010088290A1

公开(公告)日：2010-08-05

申请号：PCT/US2010/022262

申请日：2010-01-27

Applicant: ARTHUR, Thomas, D. ,  ZHU, Zhen ,  BHATTACHARYA, Sumit ,  DE HAAG, Maarten, Uijt ,  SCHEFF, Kim, Michael

Inventor： ARTHUR, Thomas, D. ,  ZHU, Zhen ,  BHATTACHARYA, Sumit ,  DE HAAG, Maarten, Uijt ,  SCHEFF, Kim, Michael

IPC: G01S5/14

CPC classification number: G01S19/45

Abstract: A method of determining the position of a user in 3D space is disclosed. In one example, the method comprises utilizing range measurements from one or more GPS satellite vehicles, angular information of a camera located at the user position, and a camera image associated with one or more known markers. The method further comprises determining the angular information of the camera by determining a direction cosine matrix between a camera frame of reference and an earth frame of reference, and designating unit vectors that individually extend from a position within the camera image associated with one of the known markers through the camera focal point to the respective known marker The method also includes integrating into an ordinary least squares matrix, the GPS range measurements, the angular information of the camera, and the unit vectors, and calculating the user position by solving the ordinary least squares matrix.

Abstract translation: 公开了一种确定用户在3D空间中的位置的方法。 在一个示例中，该方法包括利用来自一个或多个GPS卫星车辆的距离测量值，位于用户位置的相机的角度信息以及与一个或多个已知标记相关联的摄像机图像。 该方法还包括通过确定相机参考系参考系和地球参考系之间的方向余弦矩阵来确定相机的角度信息，以及指定单元向量，其从相机图像内的与已知 通过相机焦点将标记通过相应的已知标记。该方法还包括将常规最小二乘矩阵，GPS范围测量，照相机的角度信息和单位向量进行集成，并且通过求解普通最小二乘法来计算用户位置 正方形矩阵。

公开(公告)号：WO2009052181A1

公开(公告)日：2009-04-23

申请号：PCT/US2008/079993

申请日：2008-10-15

Applicant: SPANSION LLC ,  BINBOGA, Evrim

Inventor： BINBOGA, Evrim

IPC: G11C16/34

CPC classification number: G11C16/0475 ,  G11C16/0491 ,  G11C16/12 ,  G11C16/24 ,  G11C16/30

Abstract: Systems (500, 530, 900) and methods (800) that control the switching transition times or profile of a ramped voltage write signal (535) used for programming or erasing at least a wordline (309) of an array (300, 920) of multi-bit and/or multi-level flash memory cells (200) are provided. In one embodiment, this goal is accomplished by applying a ramped or otherwise controlled profile write voltage (535) to the flash memory cells (304) in order to avoid disturb issues to the unselected (non-targeted) neighboring memory cells (305), which preserves the existing state of the neighboring cells (305) while keeping the design as compact and manageable as possible yet maintains a high write speed. The systems and method are applicable to, and reliable for various memory technologies, since the size of the steps or other such functional transitions of the ramped voltage profile (535) can be adjusted or trimmed (590) to any level of resolution required.

Abstract translation: 用于控制用于对阵列（300,920）的至少一个字线（309）进行编程或擦除的斜坡电压写入信号（535）的切换转换时间或轮廓的系统（500,530,900）和方法（800） 的多位和/或多级闪存单元（200）。 在一个实施例中，该目标是通过将斜坡或其它方式控制的配置文件写入电压（535）应用于闪速存储器单元（304）来实现的，以便避免对未选定（非目标）相邻存储器单元（305）的干扰问题， 其保持相邻小区（305）的现有状态，同时保持设计尽可能紧凑和可管理，同时保持高写入速度。 系统和方法适用于各种存储器技术并且可靠，因为可以将斜坡电压分布（535）的步长或其他此类功能转换的大小调整或修整（590）至任何所需分辨率水平。

公开(公告)号：WO2008076656A1

公开(公告)日：2008-06-26

申请号：PCT/US2007/086647

申请日：2007-12-06

Applicant: SPANSION LLC ,  YANG, Nian ,  WU, Yonggang ,  YANG, Tien-chun

Inventor： YANG, Nian ,  WU, Yonggang ,  YANG, Tien-chun

IPC: G11C16/34

CPC classification number: G11C16/3404 ,  G11C16/0475

Abstract: One embodiment of the invention relates to a method (500) for accessing a memory cell (400). In this method, at least one bit of the memory cell is erased in block (506). After erasing the at least one bit, a soft program operation is performed in block (508) to bias the memory cell thereby improving the reliability of data stored in the memory cell. Other methods and systems are also disclosed.

Abstract translation: 本发明的一个实施例涉及一种用于访问存储器单元（400）的方法（500）。 在该方法中，块（506）中擦除存储单元的至少一位。 在擦除至少一个位之后，在块（508）中执行软编程操作以偏置存储器单元，从而提高存储在存储单元中的数据的可靠性。 还公开了其它方法和系统。

公开(公告)号：WO2020050921A1

公开(公告)日：2020-03-12

申请号：PCT/US2019/043176

申请日：2019-07-24

Applicant: INTEL CORPORATION

Inventor： CALLENDER, Steven ,  HULL, Christopher ,  PELLERANO, Stefano ,  SHIN, Woorim ,  KWOK, Ka Chun

IPC: H04B1/44

Abstract: A transmit receive switch (TRSW) system is disclosed. The system has a transmission line, a transformer based matching network, a shunt switch, an amplifier and circuitry. The transmission line is connected to an antenna port. The transformer based matching network is connected to the transmission line and has a first coil and a second coil, wherein the second coil is connected to the transmission line. The amplifier can be configured as a shunt switch when inactive. The shunt switch, including the amplifier configured as the shunt switch, can be connected to the first coil of the transformer based matching network. The circuitry is configured to cause the shunt switch to be ON during an inactive mode and create a short across the first coil. Combined, the length of transmission line needed to complete the impedance transformation is reduced, thereby lowering the overall insertion loss of the transmit/receive switch.

公开(公告)号：WO2019139567A1

公开(公告)日：2019-07-18

申请号：PCT/US2018/013072

申请日：2018-01-10

Applicant: INTEL CORPORATION

Inventor： KENOUN, Robert

IPC: H01Q1/27 ,  H01Q1/44

CPC classification number: H01Q1/273 ,  H01Q1/44

Abstract: An antenna structure associated with a wireless communication device comprised of a plurality of structures configured to enable structural, functional or cosmetic functions associated with the device, is proposed in this disclosure. The antenna structure comprises a first plate comprised of a first set of structures of the plurality of structures of the device and a second, different, plate comprised of a second set of structures of the plurality of structures of the device. The antenna structure further comprises an excitation component coupled between the first plate and the second plate. In some embodiments, the first plate, the second plate and at least a part of the excitation component are configured to form a tank circuit, thereby enabling the antenna structure to radiate at a predefined radiation frequency comprising a resonant frequency associated with the tank circuit.

公开(公告)号：WO2019117888A1

公开(公告)日：2019-06-20

申请号：PCT/US2017/066066

申请日：2017-12-13

Applicant: INTEL IP CORPORATION

Inventor： KUSHNIR, Igal ,  ZUR, Sarit ,  BEN-BASSAT, Assaf ,  GORDON, Eshel ,  HORWITZ, Lior ,  LANGER, Andreas ,  KRAUT, Gunther

IPC: H03F1/32 ,  H03F1/02 ,  H03F3/195 ,  H03F3/213 ,  H03F3/24

CPC classification number: H03F1/3247 ,  H03F1/0227 ,  H03F1/3258 ,  H03F3/195 ,  H03F3/213 ,  H03F3/245 ,  H03F2200/102 ,  H03F2200/228 ,  H03F2200/321 ,  H03F2200/451 ,  H03F2200/462 ,  H03F2200/468 ,  H03F2200/471 ,  H03F2201/3227 ,  H03F2201/3233

Abstract: A multi-feed predistorter circuit associated with a power amplifier (PA) system is disclosed. The multi-feed predistorter circuit comprises one or more processors configured to receive an input signal associated with the PA system. The one or more processors is further configured to receive one or more PA measurement signals comprising one or more measured parameter values, respectively associated with a PA circuit in the PA system and generate a predistorted input signal to compensate for non-linearities associated with the PA circuit, based on the input signal and the one or more PA measurement signals. In some embodiments, the one or more measured parameter values comprises measured parameter values that are different from measured parameter values associated with a PA output signal and a PA input signal of the PA circuit.

公开(公告)号：WO2018201005A1

公开(公告)日：2018-11-01

申请号：PCT/US2018/029878

申请日：2018-04-27

Applicant: INTEL IP CORPORATION

Inventor： HE, Hong ,  DAVYDOV, Alexei ,  XIONG, Gang ,  KWON, Hwan-Joon ,  CUI, Jie ,  CHATTERJEE, Debdeep ,  NIMBALKER, Ajit ,  CHO, Joonyoung ,  LEE, Dae Won

IPC: H04L1/16 ,  H04L1/18

Abstract: Methods and architectures to reduce latency in next generation wireless networks such as LTE and/or new radio (NR), includes adjusting hybrid automatic repeat request (HARQ) techniques to selectively skip acknowledgements (ACKs) in various embodiments, and to configure one or more code block groups (CBG) designating code blocks for retransmission according to a code block group index bitmap present in received downlink control information (DCI).

公开(公告)号：WO2018182606A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/024962

申请日：2017-03-30

Applicant: INTEL IP CORPORATION

Inventor： KLINKAN, Alexander ,  PFANN, Eugen

IPC: H04L27/36 ,  H04B1/04

Abstract: An apparatus for interpolation of polar signals in RF transmitters is disclosed. The apparatus comprises an estimation circuit configured to receive an input in-phase (I) quadrature (Q) signal comprising a plurality of input IQ samples having a first sampling rate associated therewith, and determine a selection metric value indicative of a position of an IQ trajectory associated with one or more input IQ samples of the input IQ signal. The apparatus further comprises a selection circuit configured to receive the input IQ signal and the selection metric value; and adaptively provide the input IQ signal to a first interpolation circuit that implements a first interpolation method or to a second interpolation circuit that implements a second, different interpolation method, for generating interpolated polar samples at a second, different sampling rate, from the input IQ signal, based on the selection metric value.

公开(公告)号：WO2018182604A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/024956

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： ZAKS, Artur

IPC: H04L29/06 ,  H04W12/06 ,  H04W84/12

Abstract: A service provider (SP) network device or system can operate to enable a WiFi protected access 2 (WPA2) pass-through with a user equipment (UE) and further define various partitions between a physical access point (pAP) and a virtual AP (vAP) according to one or more VNFs based on one or more communication link parameters (e.g., latency). The WPA2 pass-through can be an interface connection that passes through a computer premise equipment (CPE) or wireless residential gateway (GW) without the CPE or GW modifying or affecting the data traffic such as by authentication or security protocol. The SP network device can receive traffic data from a UE through or via the WPA 2 pass-through from a UE of a community Wi-Fi network at a home, residence, or entity network.