公开(公告)号：WO2022027947A1

公开(公告)日：2022-02-10

申请号：PCT/CN2021/075455

申请日：2021-02-05

Applicant: 长鑫存储技术有限公司

Inventor： 寗树梁

IPC: G11C7/10 ,  G11C11/4076

Abstract: 本发明提供一种存储系统，其包括多个存储芯片，每一所述存储芯片包括数据输出单元，所述数据输出单元共用电源及接地端，所述数据输出单元包括：上拉单元，具有控制端、第一端及第二端，第一输入信号输入至所述控制端，所述第一端与电源电连接，所述第二端连接所述数据输出单元的输出端，所述上拉单元为第一NMOS管；下拉单元，具有控制端、第一端及第二端，第二输入信号输入至所述控制端，所述第一端与接地端电连接，所述第二端连接所述数据输出单元的输出端。本发明优点是，提升数据传输速度，提高存储系统的性能，所述存储芯片的数据输出单元共用电源及接地端，从而能够简化版图布局，提高空间利用率。

公开(公告)号：WO2021206903A1

公开(公告)日：2021-10-14

申请号：PCT/US2021/023700

申请日：2021-03-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WU, Di ,  BELL, Debra M. ,  VECHES, Anthony D. ,  REHMEYER, James S. ,  WANG, Libo

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/408 ,  G06F3/06 ,  G11C7/10

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for command/address tracking in memory. Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

公开(公告)号：WO2021206892A1

公开(公告)日：2021-10-14

申请号：PCT/US2021/023250

申请日：2021-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WU, Di ,  VECHES, Anthony D. ,  REHMEYER, James S. ,  BELL, Debra M. ,  WANG, Libo

IPC: G11C11/4093 ,  G06N3/08 ,  G06F3/06 ,  G11C11/4076 ,  G11C7/10

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods for performing operations associated with machine learning. Machine learning operations may include processing a data set, training a machine learning algorithm, and applying a trained algorithm to a data set. Some of the machine learning operations, such as pattern matching operations, may be performed within a memory device.

公开(公告)号：WO2021173338A1

公开(公告)日：2021-09-02

申请号：PCT/US2021/017228

申请日：2021-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： REHMEYER, James S. ,  WANG, Libo ,  VECHES, Anthony D. ,  BELL, Debra M. ,  WU, Di

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G06F3/06

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register, lire result of the pattern matching operation may be provided by the memory. The data may be retrieved from a memory array for the pattern matching operation by a read operation, a refresh operation, an error correction operation, and/or a pattern matching operation. The data may be retrieved from incoming data input lines instead of or in addition to the memory array. How the data is stored or retrieved for pattern matching operations may be controlled by a memory controller.

公开(公告)号：WO2021158522A1

公开(公告)日：2021-08-12

申请号：PCT/US2021/016176

申请日：2021-02-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HOLLIS, Timothy, M. ,  REHMEYER, James, S. ,  CHOI, Baekkyu ,  SHARMA, Yogesh ,  STAVE, Eric, J. ,  HUBER, Brian, W. ,  WISCOMBE, Miles, S.

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G06F3/06

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

公开(公告)号：WO2020131528A1

公开(公告)日：2020-06-25

申请号：PCT/US2019/065787

申请日：2019-12-11

Applicant: RAMBUS INC.

Inventor： NIKOUKARY, Shahram ,  CHO, Jonghyun ,  JAI, Anand ,  BATRA, Pradeep ,  LUO, Lei

IPC: G11C11/4076 ,  G11C7/22 ,  G06F13/00

Abstract: A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.

公开(公告)号：WO2020009735A1

公开(公告)日：2020-01-09

申请号：PCT/US2019/026977

申请日：2019-04-11

Applicant: INTEL CORPORATION

Inventor： AGRAWAL, Abhishek ,  PELLERANO, Stefano ,  SAGAZIO, Peter ,  WANG, Yanjie

IPC: G11C7/22 ,  G11C11/4076 ,  H04L7/033 ,  G06F1/04

Abstract: In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enable signals and digital bit values. A phase modulator may include a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal, and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal, and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.

公开(公告)号：WO2019245613A1

公开(公告)日：2019-12-26

申请号：PCT/US2019/020785

申请日：2019-03-05

Applicant: MICRON TECHNOLOGY, INC

Inventor： LIU, Ming-Bo ,  PENNEY, Daniel B.

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C7/22

Abstract: Systems and methods include capture circuitry configured to capture a write signal from a host device using a data strobe signal from the host device and to output one or more indications of capture of the write signal. Calculation circuitry is configured to receive the data strobe signal, receive the one or more indications of capture, and determine a delay between a first edge of the data strobe signal and receipt of the one or more indications of capture. The systems and methods also include transmission and control circuitry configured to launch subsequent write signals at a time based at least in part on the delay.

公开(公告)号：WO2019046032A1

公开(公告)日：2019-03-07

申请号：PCT/US2018/047172

申请日：2018-08-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LEA, Perry V. ,  FINKBEINER, Timothy P.

IPC: G06F13/16 ,  G06F3/06 ,  G11C7/06 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4076

Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.

公开(公告)号：WO2016168602A3

公开(公告)日：2016-12-15

申请号：PCT/US2016027761

申请日：2016-04-15

Applicant: QUALCOMM INC

Inventor： CHUN DEXTER TAMIO ,  KIM JUNG PILL ,  LI YANRU

IPC: G11C11/406 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/50

CPC classification number: G11C11/40626 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C29/36 ,  G11C29/42 ,  G11C29/50016 ,  G11C2207/2245 ,  G11C2211/4062

Abstract: A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.

Abstract translation: 公开了一种刷新动态随机存取存储器（DRAM）的系统和方法。 一种器件包括通过总线耦合到DRAM的DRAM，总线和片上系统（SOC）。 SOC被配置为基于DRAM的温度以基于在SOC耦合到DRAM时执行的一个或多个校准测试确定的校准数据以特定刷新速率刷新DRAM。