公开(公告)号：WO2021141797A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/067261

申请日：2020-12-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CHOI, Baekkyu ,  KINSLEY, Thomas, H. ,  BADRIEH, Fuad

IPC: G11C5/14 ,  G11C5/04 ,  G06F1/3225 ,  G06F1/30

Abstract: A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.

公开(公告)号：WO2022120323A1

公开(公告)日：2022-06-09

申请号：PCT/US2021/072579

申请日：2021-11-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KINSLEY, Thomas, H. ,  CHOI, Baekkyu ,  BADRIEH, Fuad

IPC: G06F1/3234 ,  G06F1/3296 ,  G11C11/4074

Abstract: Methods, systems, and devices for memory device power management are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating one or more memory dies of the apparatus based on a supply voltage received by the memory die. The second voltage may be distributed to the one or more other memory dies in the apparatus.

公开(公告)号：WO2021158522A1

公开(公告)日：2021-08-12

申请号：PCT/US2021/016176

申请日：2021-02-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HOLLIS, Timothy, M. ,  REHMEYER, James, S. ,  CHOI, Baekkyu ,  SHARMA, Yogesh ,  STAVE, Eric, J. ,  HUBER, Brian, W. ,  WISCOMBE, Miles, S.

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G06F3/06

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

公开(公告)号：WO2021141793A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/067211

申请日：2020-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CHOI, Baekkyu ,  KINSLEY, Thomas H. ,  BADRIEH, Fuad

IPC: G11C5/14 ,  G11C5/04 ,  G06F1/3225 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/4074

Abstract: Methods, systems, and devices for feedback for power management of a memory die using shorting are described. A memory device may short a first rail with a voltage source for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device may detect a condition of one or more voltage rails for delivering power coupled with the array of memory cells. The memory device may short a first rail of the network of components for delivering power with a voltage source based on detecting the condition. In some cases, the memory device may generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.

公开(公告)号：WO2020205184A1

公开(公告)日：2020-10-08

申请号：PCT/US2020/022042

申请日：2020-03-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BADRIEH, Fuad ,  CHOI, Baekkyu ,  KINSLEY, Thomas, H.

IPC: G06F1/3234 ,  G06F1/3225 ,  G06F1/3237

Abstract: Methods, systems, and devices for predictive power management are described. Correlations may be identified between a set of commands performed at the memory device and oscillating voltage patterns, or a resonance frequency, or both. Voltages may be monitored by the memory device and be compared to the identified voltage pattern to mitigate undesirable oscillating voltages and resonance frequency.

公开(公告)号：WO2022120324A1

公开(公告)日：2022-06-09

申请号：PCT/US2021/072580

申请日：2021-11-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KINSLEY, Thomas H. ,  CHOI, Baekkyu ,  BADRIEH, Fuad

IPC: G06F1/3234 ,  G06F1/3225 ,  G11C11/4074

Abstract: Methods, systems, and devices for power management for a memory device are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating a set of memory dies of the apparatus based on a supply voltage received by the memory die. The voltage may be distributed to the set of memory dies in the apparatus.

公开(公告)号：WO2021141792A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/067184

申请日：2020-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CHOI, Baekkyu ,  BADRIEH, Fuad ,  KINSLEY, Thomas, H.

IPC: G11C5/14 ,  G11C5/04 ,  H01L23/498 ,  G06F13/16 ,  G06F1/3225 ,  G11C16/30 ,  G11C5/145 ,  G11C5/147

Abstract: Methods, systems, and devices for power regulation for memory systems are described. In one example, a memory system, such as a memory module, may include a substrate, and an input/output component coupled with the substrate and operable to communicate signals with a host system. The memory system may also include one or more memory devices coupled with the substrate and the input/output component and operable to store data for the host system. A memory device of the one or more memory devices may include a power management component in its package with one or more memory dies. The power management component may be coupled with the one or more memory dies, and feedback component, and may be operable to provide one or more supply voltages for the one or more memory dies based on one or more voltages associated with the memory system.