公开(公告)号：WO03054918A2

公开(公告)日：2003-07-03

申请号：PCT/DE0204348

申请日：2002-11-27

Applicant: INFINEON TECHNOLOGIES AG ,  JANKE MARCUS ,  LIPPMANN BERNHARD

Inventor： JANKE MARCUS ,  LIPPMANN BERNHARD

IPC: G11C5/14 ,  G11C16/22 ,  H01L

CPC classification number: G11C5/143 ,  G11C16/225

Abstract: The invention relates to a semiconductor chip whereby the programming voltage is generated on the chip and a sensor or detector is arranged in the circuit, by means of which the generation of the programming voltage in the chip is checked. The circuit arrangement comprises a transistor (1) or an XOR gate, by means of which a signal (S) is transmitted to a control unit, should the programming voltage (HV) be incorrect. It is thus possible to recognise technical defects or prevent or frustrate targeted attacks on the functioning of the chip. The invention further relates to use of the above for chipcards with a memory.

Abstract translation: 在半导体芯片中，在芯片上产生的编程电压，并在电路中，一个传感器或检测器与所述编程电压的产生也将在芯片上验证集成。 该电路装置包括一个晶体管（1）或XOR门被充电的信号（S）输出到控制单元，如果编程电压（HV）是不正确的。 这使得它能够检测技术缺陷或防止对芯片的功能，有针对性的攻击或阻挠。 使用芯片卡的内存。

公开(公告)号：WO02011289A1

公开(公告)日：2002-02-07

申请号：PCT/US2001/040935

申请日：2001-06-11

IPC: G06F21/22 ,  G06F12/14 ,  G06F21/00 ,  H03K19/173 ,  H03K19/177 ,  H04L9/10 ,  G11C16/22

CPC classification number: G06F21/76 ,  G06F12/1433 ,  G06F21/606 ,  G06F21/74 ,  G06F21/79 ,  G06F2221/2105 ,  G06F2221/2143 ,  H03K19/17704 ,  H03K19/17768

Abstract: A programmable logic chip (21) and configuration memory chip (23) are mounted within a multi-chip module (25) to form a single package. The configuration memory has a security bit (24) which in a first state allows programming a read-back of configuration data in the memory chip via external pins (29) of the package, and in a second state allows only erase command to be communicated to the memory chip via the external pins. The internal data transfer connection (27) between the memory chip and programmable logic chip is enabled when the security bit is in the second state and the memory chip is in a read-back mode, allowing configuration data to be loaded into the logic chip upon power up.

Abstract translation: 可编程逻辑芯片（21）和配置存储器芯片（23）安装在多芯片模块（25）内以形成单个封装。 配置存储器具有安全位（24），其处于第一状态允许通过封装的外部引脚（29）对存储器芯片中的配置数据进行读回编程，并且在第二状态仅允许擦除命令被传送 通过外部引脚到存储器芯片。 当安全位处于第二状态并且存储器芯片处于回读模式时，存储器芯片和可编程逻辑芯片之间的内部数据传输连接（27）被使能，允许将配置数据加载到逻辑芯片中 充电。

公开(公告)号：WO02009120A1

公开(公告)日：2002-01-31

申请号：PCT/IB2001/001289

申请日：2001-07-19

IPC: G06F12/16 ,  G06F11/14 ,  G06K19/073 ,  G11C16/10 ,  G11C16/22

CPC classification number: G11C16/102 ,  G06F11/1435 ,  G11C16/22

Abstract: A data processor, such as, for example, a smart card, comprises a controller for managing a file wherein a plurality of records can be stored in a sequential fashion. The controller checks whether a record has correctly been written into the file. The controller prevents user-related software from reading the record that is subsequent to the last record that has correctly been written.

Abstract translation: 数据处理器，例如智能卡，包括用于管理文件的控制器，其中多个记录可以以顺序的方式存储。 控制器检查记录是否已正确写入文件。 控制器阻止用户相关软件读取正确写入的最后一条记录之后的记录。

公开(公告)号：WO02005098A1

公开(公告)日：2002-01-17

申请号：PCT/AU2001/000815

申请日：2001-07-06

IPC: G06F21/55 ,  G06F21/62 ,  G06F21/79 ,  G11C16/22 ,  G06F12/14

CPC classification number: G06F21/6209 ,  G06F21/552 ,  G06F21/79 ,  G06F2221/2105 ,  G06F2221/2143 ,  G11C16/22

Abstract: A secure data storage device (1) having data storage memory (6) and an access control circuit (4). The access control circuit (4) maintains an attempt count of invalid access attempts and an access account of valid accesses to the memory (6). The access control circuit (4) disables access to the memory (6) when the attempt count or the access count exceeds a respective predetermined value. The counts are maintained in memory cells with fusible links.

Abstract translation: 一种具有数据存储器（6）和访问控制电路（4）的安全数据存储装置（1）。 访问控制电路（4）保持无效访问尝试的尝试次数和对存储器（6）的有效访问的访问帐户。 当尝试次数或访问次数超过相应的预定值时，访问控制电路（4）禁止访问存储器（6）。 这些计数被保存在具有可熔链接的存储器单元中。

公开(公告)号：WO01099113A1

公开(公告)日：2001-12-27

申请号：PCT/FR2001/001891

申请日：2001-06-18

IPC: G06F12/14 ,  G06F21/06 ,  G06F21/24 ,  G06K19/073 ,  G11C16/02 ,  G11C16/22 ,  G06F1/00

CPC classification number: G11C16/22

Abstract: The invention concerns a circuit for detecting the use (100) of an integrated circuit element. The invention is characterised in that the circuit (100) comprises: a non-volatile electrically programmable storage circuit (116) and a programming circuit (110) for partly programming said storage circuit and gradually modifying its programming level every time the element is being used, so that said level should represent the number of times it has been used.

Abstract translation: 本发明涉及用于检测集成电路元件的使用（100）的电路。 本发明的特征在于，电路（100）包括：非易失性电可编程存储电路（116）和编程电路（110），用于对所述存储电路进行部分编程，并在每次使用元件时逐渐修改其编程电平 ，所以该级别应该代表它被使用的次数。

公开(公告)号：WO01061692A1

公开(公告)日：2001-08-23

申请号：PCT/SG2000/000029

申请日：2000-02-21

IPC: G06F12/14 ,  G06F3/06 ,  G06F3/08 ,  G06F13/00 ,  G06F21/00 ,  G06F21/02 ,  G06F21/24 ,  G06K19/07 ,  G06K19/073 ,  G11B11/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22

CPC classification number: G06F21/31 ,  G06F3/0601 ,  G06F3/0605 ,  G06F3/0634 ,  G06F3/0679 ,  G06F21/12 ,  G06F21/78 ,  G06F21/79 ,  G06F21/85 ,  G06F2003/0694 ,  G06F2221/2141 ,  G11C16/102 ,  G11C16/22

Abstract: A portable data storage device (10) includes a universal serial bus (USB) coupling device (1) and an interface device (2) is coupled to the USB coupling device (1). The portable data storage device (10) also includes a memory control device (3) and a non-volatile solid-state memory device (4). The memory control device (3) is coupled between the interface device (2) and the memory device (4) to control the flow of data from the memory device (4) to the USB coupling device (1).

Abstract translation: 便携式数据存储设备（10）包括通用串行总线（USB）耦合设备（1），并且接口设备（2）耦合到USB耦合设备（1）。 便携式数据存储装置（10）还包括存储器控制装置（3）和非易失性固态存储装置（4）。 存储器控制装置（3）耦合在接口装置（2）和存储装置（4）之间，以控制从存储装置（4）到USB耦合装置（1）的数据流。

公开(公告)号：WO00075759A1

公开(公告)日：2000-12-14

申请号：PCT/US2000/015987

申请日：2000-06-08

IPC: G06F1/00 ,  G06F12/14 ,  G06F21/00 ,  G11C16/22

CPC classification number: G06F21/572 ,  G06F8/66 ,  G06F12/1408 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72 ,  G06F21/73 ,  G06F21/74 ,  G06F2207/7219 ,  G06F2221/2105 ,  G06F2221/2129 ,  G06F2221/2147

Abstract: Methods and an apparatus for storing information in a processing device with flexible security are disclosed. In one embodiment, a method stores information within the processing device. The method receives a download via a first input path which includes a first breakable link and stores the donwload within the processing device. At some point, a key is also stored within the processing device. A ciphertext download is received via a second input path which includes a second breakable link. The ciphertext download is decrypted utilizing the key and the resulting plaintext download is stored within the processing device.

Abstract translation: 公开了一种在具有灵活安全性的处理设备中存储信息的方法和装置。 在一个实施例中，方法将信息存储在处理设备内。 该方法经由包括第一可破坏链路的第一输入路径接收下载，并将该不负载存储在处理设备内。 在某一点上，密钥也存储在处理设备内。 经由包括第二可破坏链路的第二输入路径接收密文下载。 使用密钥对密文下载进行解密，并将所得到的明文下载存储在处理设备内。

公开(公告)号：WO00054282A1

公开(公告)日：2000-09-14

申请号：PCT/US2000/006165

申请日：2000-03-09

IPC: G06F15/78 ,  G06F9/24 ,  G06F9/30 ,  G11C16/22 ,  G06F1/22 ,  G11C29/00

CPC classification number: G11C16/225 ,  G06F9/24 ,  G06F9/30101 ,  G11C16/22

Abstract: A microcontroller having a memory programmable in user mode. The microcontroller contains circuitry for detecting whether a programming level voltage has been activated. Also included is a Longwrite enable register containing an enable bit for enabling/disabling programming of the memory. When the register contains the bit indicating programming as enabled, and the programming level voltage is detected, the microcontroller allows the program memory to be programmed. The programming can take place in user mode. The programming level voltage signal is also used to detect whether to enter into a test mode. Programming of the program memory is also possible in the test mode. The invention is also directed to a method for operating a microcontroller for controlling programming of the program memory. The microcontroller according to the invention allows increased functionality by detecting whether to enter the test mode without the requirement of a test mode select input signal.

Abstract translation: 具有可在用户模式下编程的存储器的微控制器。 微控制器包含用于检测编程电平电压是否被激活的电路。 还包括一个Longwrite使能寄存器，其中包含启用/禁用存储器编程的使能位。 当寄存器包含指示编程使能的位，并且检测到编程电平电压时，微控制器允许对程序存储器进行编程。 编程可以在用户模式下进行。 编程电平电压信号也用于检测是否进入测试模式。 程序存储器的编程在测试模式下也是可能的。 本发明还涉及一种用于操作微控制器以控制程序存储器的编程的方法。 根据本发明的微控制器通过检测是否进入测试模式而允许增加的功能，而不需要测试模式选择输入信号。

公开(公告)号：WO99046774A1

公开(公告)日：1999-09-16

申请号：PCT/US1999/005049

申请日：1999-03-09

IPC: G11C7/24 ,  G11C16/22 ,  H04L9/18 ,  G11C7/00

CPC classification number: G11C7/24 ,  G11C16/22 ,  H04L9/065 ,  H04L2209/12

Abstract: A decryption scheme is provided for encrypted configuration bitstreams in a programmable logic device. One embodiment includes circuitry for altering a decryption key for a plurality of encrypted bitstream portions, thereby providing a high level of security of the circuit layout embodied in the bitstream.

Abstract translation: 为可编程逻辑器件中的加密配置比特流提供解密方案。 一个实施例包括用于改变多个加密的比特流部分的解密密钥的电路，从而提供在比特流中体现的电路布局的高水平的安全性。

公开(公告)号：WO99018504A1

公开(公告)日：1999-04-15

申请号：PCT/US1998/019944

申请日：1998-09-23

IPC: B42D15/10 ,  G06F12/14 ,  G06F21/02 ,  G06F21/24 ,  G06K19/07 ,  G06K19/10 ,  G07F7/10 ,  G11C16/22 ,  G06F11/00 ,  G06F7/04 ,  G07D7/00

CPC classification number: G07F7/1008 ,  G06F12/1441 ,  G06Q20/341 ,  G06Q20/35765

Abstract: According to the present invention, a secured memory (20) comprises a first level security zone (22) having an access code (SCI) controlling access to the secured memory (20) prior to an issuer fuse (28) being blown, a security code attempts counter (SLAC) preventing access to the secured memory (20) when a predetermined number of attempts at matching the access code have been made prior to resetting the security code attempts counter (SCAC), a plurality of application zones (24), each of the plurality of application zones comprising: a storage memory zone (SMZ 2-4), an application security zone (24) having an application zone access code (SC2-4) controlling access to the storage memory zone after an issuer fuse (28) has been blown, an application zone security code attempts counter (S2-4AC) preventing access to the application zone (24) when a predetermined number of attempts at matching the application zone access code (SC2-4) have been made prior to resetting the application zone security code attempts counter, an erase key (EZ2-4) partition having an erase key code controlling erase access counter (E1-4AC) preventing erase access to the application zone when a predetermined number of attempts at matching the erase key code (EZ2-4) have been made prior to resetting the erase key attempts counter (E1-4AC).

Abstract translation: 根据本发明，一种安全存储器（20）包括一个第一级安全区（22），该第一级安全区（22）具有访问代码（SCI），该访问代码在发布者熔断器（28）被吹制之前控制对所述安全存储器（20）的访问， 当在安全代码尝试计数器（SCAC），多个应用区域（24），复位计数器（24）之前已经进行了匹配访问代码的预定次数的尝试时，代码尝试计数器（SLAC）阻止访问安全存储器（20） 所述多个应用区域中的每一个包括：存储存储区域（SMZ 2-4），具有在发布者熔断器之后控制对存储存储区域的访问的应用区域访问代码（SC2-4）的应用安全区域（24） 28）已经被吹制，当在匹配应用区域访问代码（SC2-4）的预定次数的尝试之前已经做出了应用区域安全代码尝试计数器（S2-4AC）以防止访问应用区域（24） 重新设置应用程序区域 理智代码尝试计数器，当预定次数的尝试匹配擦除密钥代码（EZ2-4）时，具有控制擦除访问计数器（E1-4AC）的擦除密钥代码的擦除密钥（EZ2-4）分区防止对应用区的擦除访问， 4）在复位擦除密钥尝试计数器（E1-4AC）之前已经进行了。