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    ENCODED ENABLE CLOCK GATERS
    1.
    发明申请
    ENCODED ENABLE CLOCK GATERS 审中-公开

    公开(公告)号：WO2023048821A1

    公开(公告)日：2023-03-30

    申请号：PCT/US2022/038560

    申请日：2022-07-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： SHYVERS, Patrick J.

    IPC: G06F3/06 ,  G11C16/10 ,  G11C11/56

    Abstract: A processing device is provided which includes a processor and a data storage structure. The data storage structure comprises a data storage array comprising a plurality of lines. Each line comprises at least one A latch configured to store a data bit and a clock gater. The data storage structure also comprises a write data B latch configured to store, over different clock cycles, a different data bit, each to be written to the at least one A latch of one of the plurality of lines. The data storage structure also comprises a plurality of write index B latches shared by the clock gaters of the lines. The write index B latches are configured to store, over the different clock cycles, combinations of index bits having values which index one of the lines to which a corresponding data bit is to be stored.

    MULTIPLE BIT MAGNORESISTIVE RANDOM ACCESS MEMORY CELL
    4.
    发明申请
    MULTIPLE BIT MAGNORESISTIVE RANDOM ACCESS MEMORY CELL 审中-公开

    公开(公告)号：WO2022236205A1

    公开(公告)日：2022-11-10

    申请号：PCT/US2022/071322

    申请日：2022-03-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： LI, Xia ,  YANG, Bin

    IPC: G11C11/16 ,  G11C11/56

    Abstract: Disclosed are examples of multiple bit magnetoresistive random access memory (MRAM) cells. A multiple bit MRAM cell may comprise a fixed layer, alternately stacked N tunnel barriers and N free layers, and a tunnel cap. N, which may represent number of bits of the MRAM cell, may be greater than or equal to two. Magnetic moment of the fixed layer may be fixed in one perpendicular direction. Magnetic moments of the free layers may be switchable from one to other perpendicular directions upon application of switch currents. The switch currents may be different for different layers. The magnetic moments of the free layers may be switched separately or otherwise independently of other free layers when the switch currents are applied separately.

    DISTRIBUTED COMPACTION OF LOGICAL STATES TO REDUCE PROGRAM TIME
    5.
    发明申请
    DISTRIBUTED COMPACTION OF LOGICAL STATES TO REDUCE PROGRAM TIME 审中-公开

    公开(公告)号：WO2022125830A1

    公开(公告)日：2022-06-16

    申请号：PCT/US2021/062698

    申请日：2021-12-09

    Applicant: MICRON TECHNOLOGY, INC. [US]/[US]

    Inventor： KAVALIPURAPU, Kalyan Chakravarthy ,  MATAMIS, George ,  DONG, Yingda ,  SIAU, Chang H.

    IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34

    Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

    半導体装置の駆動方法
    7.
    发明申请
    半導体装置の駆動方法 审中-公开

    公开(公告)号：WO2022029534A1

    公开(公告)日：2022-02-10

    申请号：PCT/IB2021/056525

    申请日：2021-07-20

    Applicant: 株式会社半導体エネルギー研究所

    Inventor： 山崎舜平 ,  木村肇 ,  國武寛司

    IPC: G11C11/22 ,  G11C11/56 ,  H01L27/11507

    Abstract: データを長期間保持することができる半導体装置を提供する。 容量と、第１のトランジスタと、第２のトランジスタと、が設けられるセルを有し、容量は、第１の電極と、第２の電極と、強誘電体層と、を有し、強誘電体層は、第１の電極と、第２の電極と、の間に設けられ、且つ第１の飽和分極電圧、又は第１の飽和分極電圧と極性が異なる第２の飽和分極電圧を印加することにより、分極反転が発生し、第１の電極と、第１のトランジスタのソース又はドレインの一方と、第２のトランジスタのゲートと、は互いに電気的に接続された半導体装置。第１の期間において、強誘電体層に、第１の飽和分極電圧を印加する。第２の期間において、強誘電体層に、第１の飽和分極電圧と、第２の飽和分極電圧と、の間の値の電圧を、データ電圧として印加する。

    QUATERNARY FIELD EFFECT TRANSISTOR
    8.
    发明申请
    QUATERNARY FIELD EFFECT TRANSISTOR 审中-公开

    公开(公告)号：WO2022015963A1

    公开(公告)日：2022-01-20

    申请号：PCT/US2021/041799

    申请日：2021-07-15

    Applicant: KKT HOLDINGS SYNDICATE

    Inventor： KUO, Tzu-Yi

    IPC: G11C11/56

    Abstract: This invention provides a quaternary field effect transistor with two gate electrodes for individually controlling a conductivity type of a channel region between a source and a drain, such that the quaternary field effect transistor is turned-on or turned-off. The quaternary field effect transistor has operations similar to logic gates, and area of one quaternary field effect transistor is close to one conventional MOSFET.

    ACCESSING A MULTI-LEVEL MEMORY CELL
    10.
    发明申请
    ACCESSING A MULTI-LEVEL MEMORY CELL 审中-公开

    公开(公告)号：WO2022010691A1

    公开(公告)日：2022-01-13

    申请号：PCT/US2021/039534

    申请日：2021-06-29

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： SARPATWARI, Karthik ,  TRAN, Xuan-Anh ,  CHEN, Jessica ,  DURAND, Jason, A. ,  GAJERA, Nevil, N. ,  LEE, Yen Chun

    IPC: G11C11/56 ,  G11C13/00 ,  H01L45/00

    Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

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