公开(公告)号：WO2021076178A1

公开(公告)日：2021-04-22

申请号：PCT/US2020/022450

申请日：2020-03-12

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： LIANG, Hsuan ,  WU, Man Tang ,  YANG, Jeng-Wei ,  CHANG, Lihsin ,  TRAN, Hieu Van ,  DO, Nhan

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  H01L29/423

Abstract: A memory cell array with memory cells arranged in rows and columns, first sub source lines each connecting together the source regions in one of the rows and in a first plurality of the columns, second sub source lines each connecting together the source regions in one of the rows and in a second plurality of the columns, a first and second erase gate lines each connecting together all of the erase gates in the first and second plurality of the columns respectively, first select transistors each connected between one of first sub source lines and one of a plurality of source lines, second select transistors each connected between one of second sub source lines and one of the source lines, first select transistor line connected to gates of the first select transistors, and a second select transistor line connected to gates of the second select transistors.

公开(公告)号：WO2019217022A1

公开(公告)日：2019-11-14

申请号：PCT/US2019/026671

申请日：2019-04-09

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： DO, Nhan ,  SU, Chien-Sheng ,  YANG, Jeng-Wei

IPC: H01L29/66 ,  H01L29/788

Abstract: A memory device includes a semiconductor substrate having spaced apart source and drain regions, with a channel region of the substrate extending there between, a floating gate of polysilicon disposed over and insulated from a first portion of the channel region by insulation material having a first thickness, wherein the floating gate has a sloping upper surface that terminates in a sharp edge, a word line gate of polysilicon disposed over and insulated from a second portion of the channel region by insulation material having a second thickness, and an erase gate of polysilicon disposed over and insulated from the source region by insulation material having a third thickness, wherein the erase gate includes a notch that wraps around and is insulated from the sharp edge of the floating gate. The third thickness is greater than the first thickness, and the first thickness is greater than the second thickness.

公开(公告)号：WO2016148873A1

公开(公告)日：2016-09-22

申请号：PCT/US2016/019860

申请日：2016-02-26

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-Sheng ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  TRAN, Hieu Van ,  DO, Nhan ,  CHEN, Chun-Ming

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Abstract translation: 一种非易失性存储单元，包括具有上表面和两个侧表面的鳍形上表面的半导体衬底。 源极和漏极区域形成在鳍状上表面部分中，其间具有沟道区域。 导电浮栅包括沿着顶表面的第一部分延伸的第一部分，以及分别沿两个侧表面的第一部分延伸的第二和第三部分。 导电控制栅极包括沿着顶表面的第二部分延伸的第一部分，分别沿着两个侧表面的第二部分延伸的第二部分和第三部分，第一部分和第二部分， 以及分别延伸至少一些所述浮动栅极第二和第三部分的第五和第六部分。

公开(公告)号：WO2015112282A1

公开(公告)日：2015-07-30

申请号：PCT/US2014/070674

申请日：2014-12-16

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-Wei ,  SU, Chien-Sheng

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L21/3088

Abstract: A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.

Abstract translation: 使用双重图案化工艺在半导体衬底中形成有源区和隔离区的方法。 该方法包括在衬底表面上形成第一材料，在第一材料上形成第二材料，在第二材料中形成多个第一沟槽，其中多个第一沟槽彼此平行，形成第二沟槽 材料，其中所述第二沟槽在所述衬底的中心区域中垂直于所述第一沟槽并与所述多个第一沟槽交叉，用第三材料填充所述第一和第二沟槽，移除所述第二材料以在所述第三材料中形成平行于所述第三材料的第三沟槽 彼此不延伸穿过衬底的中心区域，并且延伸第三沟槽穿过第一材料并进入衬底。

公开(公告)号：WO2017078918A1

公开(公告)日：2017-05-11

申请号：PCT/US2016/057222

申请日：2016-10-14

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： ZHOU, Feng ,  LIU, Xian ,  YANG, Jeng-Wei ,  DO, Nhan

IPC: G11C16/04 ,  H01L21/336 ,  H01L21/8239 ,  H01L29/778 ,  H01L29/788

CPC classification number: H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66825

Abstract: A non-volatile memory cell that includes a silicon substrate, source and drain regions formed in the silicon substrate (where a channel region of the substrate is defined between the source and drain regions), a metal floating gate disposed over and insulated from a first portion of the channel region, a metal control gate disposed over and insulated from the metal floating gate, a polysilicon erase gate disposed over and insulated from the source region, and a polysilicon word line gate disposed over and insulated from a second portion of the channel region.

Abstract translation: 包括硅衬底，在硅衬底中形成的源极区和漏极区（其中在衬底的沟道区限定在源极区和漏极区之间）的非易失性存储器单元，金属浮动 栅极，设置在沟道区域的第一部分之上并与之绝缘;金属控制栅极，设置在金属浮动栅极之上并与其绝缘;多晶硅擦除栅极，设置在源极区域之上并与之绝缘;以及多晶硅字线栅极， 与沟道区域的第二部分绝缘。

公开(公告)号：WO2017070018A1

公开(公告)日：2017-04-27

申请号：PCT/US2016/057101

申请日：2016-10-14

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： CHEN, Chun-Ming ,  WU, Man-Tang ,  YANG, Jeng-Wei ,  SU, Chien-Sheng ,  DO, Nhan

IPC: G11C16/02 ,  G11C11/34 ,  G06F13/00

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788

Abstract: A method of forming a non- volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.

Abstract translation: 形成非易失性存储器单元的方法包括在衬底中形成间隔开的第一区域和第二区域，在其间限定沟道区域。 浮置栅极形成在沟道区域的第一部分之上以及第一区域的一部分之上，其中浮置栅极包括布置在第一区域之上的尖锐边缘。 隧道氧化层围绕尖锐边缘形成。 擦除栅极形成在第一区域上方，其中擦除栅极包括面向尖锐边缘的凹口，并且其中凹口通过隧道氧化物层与尖锐边缘绝缘。 字线门形成在与第二区域相邻的沟道区域的第二部分之上。 字线门的形成是在形成隧道氧化层和擦除门之后进行的。

公开(公告)号：WO2016118785A1

公开(公告)日：2016-07-28

申请号：PCT/US2016/014393

申请日：2016-01-21

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-Wei ,  CHEN, Chun-Ming ,  WU, Man-Tang ,  ZHOU, Feng ,  LIU, Xian ,  SU, Chien-Sheng ,  DO, Nhan

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

Abstract translation: 一种通过形成间隔开的第一和第二区域形成存储器件的方法，其间具有通道区域，在沟道区域的第一部分上方形成浮栅，并与沟道区域的第一部分绝缘，形成控制栅极并与浮栅绝缘，形成 擦除栅极，并与第一区域绝缘，并且形成选通栅极，并与沟道区域的第二部分绝缘。 浮置栅极的形成包括在衬底上形成第一绝缘层，在第一绝缘层上形成第一导电层，并执行两个单独的蚀刻以形成通过第一导电层的第一和第二沟槽。 第一沟槽处的第一导电层的侧壁具有负斜率，第二沟槽处的第一导电层的侧壁是垂直的。

公开(公告)号：WO2022010546A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/019297

申请日：2021-02-23

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-Wei ,  WU, Man Tang ,  FAN, Boolean ,  DO, Nhan

IPC: H01L27/11521 ,  H01L29/423 ,  H01L21/28

Abstract: A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.

公开(公告)号：WO2019221867A1

公开(公告)日：2019-11-21

申请号：PCT/US2019/027760

申请日：2019-04-16

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： LIANG, Hsuan ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  DO, Nhan ,  TRAN, Hieu, Van

IPC: G11C16/16 ,  G11C16/04

Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

公开(公告)号：WO2019112756A1

公开(公告)日：2019-06-13

申请号：PCT/US2018/060181

申请日：2018-11-09

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-Wei ,  WU, Man-Tang ,  CHEN, Chun-Ming ,  SU, Chien-Sheng ,  DO, Nhan

IPC: G11C16/04 ,  H01L27/115

Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.