公开(公告)号：WO2007031696A1

公开(公告)日：2007-03-22

申请号：PCT/GB2005/003531

申请日：2005-09-13

Applicant: ARM LIMITED ,  GHOSH, Mrinmoy ,  ÖZER, Emre ,  BILES, Stuard, David

Inventor： GHOSH, Mrinmoy ,  ÖZER, Emre ,  BILES, Stuard, David

IPC: G06F12/08 ,  G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/383 ,  G06F12/0802 ,  G06F12/0897

Abstract: A data processing apparatus and method are provided for detecting cache misses. The data processing apparatus has processing logic for executing a plurality of program threads, and a cache for storing data values for access by the processing logic. When access to a data value is required while executing a first program thread, the processing logic issues an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure to determine whether the data value is stored in the cache. Indication logic is provided which in response to an address portion of the address provides an indication as to whether the data value is stored in the cache, this indication being produced before a result of the lookup procedure is available, and the indication logic only issuing an indication that the data value is not stored in the cache if that indication is guaranteed to be correct. Control logic is then provided which, if the indication indicates that the data value is not stored in the cache, uses that indication to control a process having an effect on a program thread other than the first program thread.

Abstract translation: 提供了一种用于检测高速缓存未命中的数据处理装置和方法。 数据处理装置具有用于执行多个程序线程的处理逻辑，以及用于存储由处理逻辑进行访问的数据值的高速缓存。 当执行第一程序线程时需要访问数据值时，处理逻辑发出指定与该数据值相关联的存储器中的地址的访问请求，并且高速缓冲存储器响应于地址执行查找过程以确定是否 数据值存储在缓存中。 指示逻辑被提供，其响应于地址的地址部分提供关于数据值是否存储在高速缓存中的指示，该指示是在查找过程的结果可用之前产生的，并且指示逻辑仅发出 指示如果该指示保证正确，则数据值不存储在高速缓存中。 然后提供控制逻辑，如果该指示指示数据值未被存储在高速缓存中，则使用该指示来控制对除第一程序线程之外的程序线程有影响的进程。

公开(公告)号：WO2013061025A1

公开(公告)日：2013-05-02

申请号：PCT/GB2012/052204

申请日：2012-09-07

Applicant: ARM LIMITED ,  ÖZER, Emre ,  SAZEIDES, Yiannakis ,  KERSHAW, Daniel ,  BILES, Stuart David

Inventor： ÖZER, Emre ,  SAZEIDES, Yiannakis ,  KERSHAW, Daniel ,  BILES, Stuart David

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/1415 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0787 ,  G06F2201/86

Abstract: A data processing apparatus and method are provided for analysing transient faults occurring within storage elements of the data processing apparatus. The data processing apparatus has a plurality of storage elements residing at different physical locations within the data processing apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry then monitors the global transient fault history data in order to determine based on predetermined criteria whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. Such an approach provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.

Abstract translation: 提供了一种用于分析在数据处理装置的存储元件内发生的瞬态故障的数据处理装置和方法。 数据处理装置具有驻留在数据处理装置内的不同物理位置处的多个存储元件，以及用于检测在每个存储元件中发生的局部瞬态故障的故障历史电路，以及用于基于检测到的局部瞬态来保持全局瞬态故障历史数据 故障。 分析电路然后监视全局瞬态故障历史数据，以便基于预定标准来确定全局瞬态故障历史数据是指示在数据处理装置内发生的随机瞬态故障，还是指示协调的瞬时故障攻击。 分析电路然后被配置为启动对协调的瞬态故障攻击的确定的对策动作。 这种方法提供了一种用于区分可能自然发生的随机瞬态故障的简单和有效的机制，以及可以在试图规避数据处理设备的安全性时发起的协调的瞬态故障攻击。

公开(公告)号：WO2009106788A1

公开(公告)日：2009-09-03

申请号：PCT/GB2008/004301

申请日：2008-12-29

Applicant: ARM LIMITED ,  DAS, Shidhartha ,  BULL, David, Michael ,  ÖZER, Emre

Inventor： DAS, Shidhartha ,  BULL, David, Michael ,  ÖZER, Emre

IPC: G01R31/3181 ,  G06F11/10

CPC classification number: G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

Abstract: An integrated circuit (2) is provided with error detection circuitry (10,12) and error repair circuitry (14). Error tolerance circuitry (16) is responsive to a control parameter to selectively disable the error repair circuitry (14). The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behaviour of the circuit or in other ways.

Abstract translation: 集成电路（2）具有错误检测电路（10,12）和错误修复电路（14）。 误差容限电路（16）响应于控制参数来选择性地禁用误差修复电路（14）。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

公开(公告)号：WO2007101969A1

公开(公告)日：2007-09-13

申请号：PCT/GB2006/000795

申请日：2006-03-06

Applicant: ARM LIMITED ,  FORD, Simon, Andrew ,  GHOSH, Mrinmoy ,  ÖZER, Emre ,  BILES, Stuart, David

Inventor： FORD, Simon, Andrew ,  GHOSH, Mrinmoy ,  ÖZER, Emre ,  BILES, Stuart, David

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F2212/1016 ,  G06F2212/6032 ,  Y02D10/13

Abstract: A data processing apparatus is provided having processing logic for performing a sequence of operations, and a cache having a plurality of segments for storing data values for access by the processing logic. The processing logic is arranged, when access to a data value is required, to issue an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure during which it is determined whether the data value is stored in the cache. Indication logic is provided which, in response to an address portion of the address, provides for each of at least a subject of the segments an indication as to whether the data value is stored in that segment. The indication logic has guardian storage for storing guarding data, and hash logic for performing a hash operation on the address portion in order to reference the guarding data to determine each indication. Each indication indicates whether the data value is either definitely not stored in the associated segment or is potentially stored with the associated segment, and the cache is then operable to use the indications produced by the indication logic to affect the lookup procedure performed in respect of any segment whose associated indication indicates that the data value is definitely not stored in that segment. This technique has been found to provide a particularly power efficient mechanism for accessing the cache.

Abstract translation: 提供了具有用于执行操作序列的处理逻辑的数据处理装置，以及具有多个段的高速缓存，用于存储由处理逻辑进行访问的数据值。 当需要访问数据值时，处理逻辑被布置为发出指定与该数据值相关联的存储器中的地址的访问请求，并且高速缓存响应于地址以执行查找过程，在此期间确定是否确定是否 数据值存储在缓存中。 提供指示逻辑，响应于地址的地址部分，为段中的至少一个对象提供关于数据值是否存储在该段中的指示。 指示逻辑具有用于存储保护数据的保护存储和用于对地址部分执行散列操作的散列逻辑，以引用保护数据来确定每个指示。 每个指示指示数据值是否绝对不存储在相关联的段中或潜在地与相关联的段相关联，并且高速缓存然后可操作以使用由指示逻辑产生的指示来影响关于任何 其相关联的指示表明数据值绝对不存储在该段中。 已经发现这种技术提供了用于访问高速缓存的特别有效的机构。