公开(公告)号：WO2009106788A1

公开(公告)日：2009-09-03

申请号：PCT/GB2008/004301

申请日：2008-12-29

Applicant: ARM LIMITED ,  DAS, Shidhartha ,  BULL, David, Michael ,  ÖZER, Emre

Inventor： DAS, Shidhartha ,  BULL, David, Michael ,  ÖZER, Emre

IPC: G01R31/3181 ,  G06F11/10

CPC classification number: G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

Abstract: An integrated circuit (2) is provided with error detection circuitry (10,12) and error repair circuitry (14). Error tolerance circuitry (16) is responsive to a control parameter to selectively disable the error repair circuitry (14). The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behaviour of the circuit or in other ways.

Abstract translation: 集成电路（2）具有错误检测电路（10,12）和错误修复电路（14）。 误差容限电路（16）响应于控制参数来选择性地禁用误差修复电路（14）。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

公开(公告)号：WO2010007367A1

公开(公告)日：2010-01-21

申请号：PCT/GB2009/001751

申请日：2009-07-15

Applicant: ARM Limited ,  KERSHAW, Daniel ,  BULL, David Michael ,  WILDER, Mladen

Inventor： KERSHAW, Daniel ,  BULL, David Michael ,  WILDER, Mladen

IPC: H04L1/20 ,  H04L1/00 ,  G06F1/32 ,  H04B7/06

CPC classification number: H04L1/20 ,  H04B7/0619 ,  H04B7/0689 ,  H04B7/0691 ,  H04B17/336 ,  H04L1/0002 ,  H04L1/0025 ,  H04L25/0202

Abstract: An electronic device is described which receives data from a transmitting device via a communications channel. The electronic device comprises digital processing circuitry arranged to process the data received via the communications channel to generate output data, error detection circuitry arranged to detect errors in the output data, and monitoring circuitry arranged to monitor the quality of digital processing conducted by the digital processing circuitry and generate digital performance data indicative of the monitored quality of digital processing. The electronic device also comprises control circuitry responsive to error information comprising errors detected by the error detection circuitry and the performance data generated by the monitoring circuitry to modify the operation of one or both of the transmitting device and the electronic device. The digital performance data provides the control circuitry with additional information for use in identifying where errors in signal processing are arising, enabling an informed decision be made to modify the operation of either the transmitting device or receiving device in some way, either to reduce the occurrence of errors in the output signal or to improve the speed and/or efficiency of the transmitter and/or receiver.

Abstract translation: 描述了经由通信信道从发送设备接收数据的电子设备。 电子设备包括数字处理电路，其被布置成处理经由通信信道接收的数据以产生输出数据，布置成检测输出数据中的错误的错误检测电路以及被设置为监视由数字处理进行的数字处理的质量的监视电路 电路并产生指示数字处理的监控质量的数字性能数据。 电子设备还包括响应于错误信息的控制电路，错误信息包括由错误检测电路检测到的错误和由监控电路产生的性能数据，以修改发送设备和电子设备中的一个或两者的操作。 数字性能数据为控制电路提供附加信息，用于识别信号处理中的错误出现位置，使得能够以某种方式做出明智的决定以修改发射设备或接收设备的操作，以减少发生 的输出信号中的错误或提高发射机和/或接收机的速度和/或效率。

公开(公告)号：WO2007063264A1

公开(公告)日：2007-06-07

申请号：PCT/GB2005/004636

申请日：2005-12-02

Applicant: ARM LIMITED ,  NEW, David ,  HOXEY, Paul, Darren ,  BULL, David, Michael ,  DAS, Shidhartha

Inventor： NEW, David ,  HOXEY, Paul, Darren ,  BULL, David, Michael ,  DAS, Shidhartha

IPC: G11C11/34

CPC classification number: G11C7/08 ,  G11C7/24 ,  G11C11/4125 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/26

Abstract: A data processing system comprising a memory array having a plurality of memory cells (240-246) and read circuitry (310,320) for reading a logic value stored in one of the plurality of memory cells. The read circuitry (310,320) is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided (330) for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.

Abstract translation: 一种数据处理系统，包括具有多个存储单元（240-246）的存储器阵列和用于读取存储在多个存储器单元之一中的逻辑值的读取电路（310,320）。 读取电路（310,320）可操作地执行存储的逻辑值的两个基本上同时的读取。 提供电压控制器并且可操作以选择性地改变对存储器阵列的电源电压的电平。 提供检测电路（330），用于根据两个基本上同时的读取来检测当电源电压电平导致读取结果不可靠时。

公开(公告)号：WO2011154719A1

公开(公告)日：2011-12-15

申请号：PCT/GB2011/051022

申请日：2011-05-31

Applicant: ARM LIMITED ,  IDGUNJI, Sachin Satish ,  DAS, Shidhartha ,  BULL, David Michael ,  AITKEN, Robert Campbell

Inventor： IDGUNJI, Sachin Satish ,  DAS, Shidhartha ,  BULL, David Michael ,  AITKEN, Robert Campbell

IPC: G06F13/40 ,  G01R31/317

CPC classification number: G01R31/3016

Abstract: An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus. The data processing apparatus includes a second sequential storage structure which is arranged to latch the output signal generated by combinatorial circuitry dependent on a second clock signal. The second sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry, and transition detection circuitry for detecting a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct. The second sequential storage structure can be operated in either a first mode of operation or a second mode of operation. In the first mode of operation, the predetermined timing window is a timing window ahead of a time at which the main storage element latches said value of the output signal, to thereby enable an approaching setup timing error due to a propagation delay within the combinatorial circuitry to be detected. In the second mode of operation, the predetermined timing window is a timing window after the time at which the main storage element latches said value of the output signal such that an approaching hold timing error due to an increase in skew between the first and second clock signals is detected. Such a technique provides a simple and efficient mechanism for detecting a variety of approaching error conditions whilst the second sequence storage structure continues to operate correctly.

Abstract translation: 提供了一种用于检测数据处理装置内接近的错误状况的装置和方法。 数据处理装置包括第二顺序存储结构，其被配置为根据第二时钟信号锁存由组合电路产生的输出信号。 第二顺序存储结构具有主存储元件，用于锁存输出信号的值以提供给后续组合电路;以及转换检测电路，用于检测由主存储元件在预定定时期间锁存的输出信号的值的变化 窗口，所述改变指示接近的错误状态，而存储在主存储元件中的值仍然是正确的。 第二顺序存储结构可以在第一操作模式或第二操作模式中操作。 在第一操作模式中，预定定时窗口是在主存储元件锁存输出信号的值的时间之前的定时窗口，从而使由于组合电路内的传播延迟引起的接近的建立定时误差 被检测。 在第二操作模式中，预定定时窗口是在主存储元件锁存输出信号的值的时间之后的定时窗口，使得由于第一和第二时钟之间的偏斜增加而接近的保持定时误差 检测到信号。 这种技术提供了一种用于检测各种接近错误状况的简单有效的机制，同时第二序列存储结构继续正确地操作。

公开(公告)号：WO2006115474A1

公开(公告)日：2006-11-02

申请号：PCT/US2005/013555

申请日：2005-04-21

Applicant: ARM LIMITED ,  UNIVERSTY OF MICHIGAN ,  BLAAUW, David, Theodore ,  BULL, David, Michael ,  DAS, Shidhartha

Inventor： BLAAUW, David, Theodore ,  BULL, David, Michael ,  DAS, Shidhartha

IPC: G06F11/14

CPC classification number: G06F11/1407

Abstract: An integrated circuit comprises an error detection circuit 3230-1 to 3230-4 operable to detect a transition in the signal value in a predetermined time window, which is indicative of an error in operation of the integrated circuit. The integrated circuit also comprises a storage unit 3296 operable to store a recoverable state of the data processing apparatus comprising at least a subset of architectural state variables corresponding to a programmer's model of the integrated circuit. An error recovery circuit 3250, 3260,3210 is provided as part of the integrated circuit and this serves to enable the integrated circuit to recover from detected errors in operation using the stored recoverable state from the storage unit 3296. An operational parameter controller 3242 of the integrated circuit adjusts the operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature in dependence upon one or more characteristics of detected errors in operation so as to maintain a finite non-zero error rate in a manner that increases overall performance.

Abstract translation: 集成电路包括错误检测电路3230-1至3230-4，其可操作以检测指示集成电路的操作中的错误的预定时间窗中的信号值中的转变。 集成电路还包括存储单元3296，其可操作以存储数据处理装置的可恢复状态，该可恢复状态包括与集成电路的编程器模型对应的架构状态变量的至少一个子集。 作为集成电路的一部分提供了错误恢复电路3250,3260,3210，并且这用于使得集成电路能够使用来自存储单元3296的存储的可恢复状态的操作中的检测到的错误恢复。 集成电路根据操作中检测到​​的错误的一个或多个特性调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度，以保持有限的非零误码率 以提高整体性能的方式。