公开(公告)号：WO2010007338A2

公开(公告)日：2010-01-21

申请号：PCT/GB2009/001503

申请日：2009-06-12

Applicant: ARM LIMITED ,  FORD, Simon, Andrew ,  HILL, Stephen, John

Inventor： FORD, Simon, Andrew ,  HILL, Stephen, John

CPC classification number: G06F9/3844 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/815 ,  G06F2201/875 ,  G06F2201/88 ,  G06F2201/885 ,  Y02B70/16 ,  Y02D10/34

Abstract: A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.

Abstract translation: 公开了一种包括用于执行数据处理过程的处理器和用于执行调谐过程的处理器的数据处理装置。 数据处理装置被布置为使得作为与数据处理过程不同的过程的调整过程可以访问数据处理过程的推测机制的参数并调整参数，使得机制以不同方式推测并且以这种方式来执行 这个数据处理过程可以改进。

公开(公告)号：WO2008007038A1

公开(公告)日：2008-01-17

申请号：PCT/GB2006/002555

申请日：2006-07-11

Applicant: ARM LIMITED ,  SYMES, Dominic, Hugo ,  REID, Alastair ,  FORD, Simon, Andrew

Inventor： SYMES, Dominic, Hugo ,  REID, Alastair ,  FORD, Simon, Andrew

IPC: G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/345 ,  G06F9/3838

Abstract: A parallel processing technique is described for performing parallel processing operations upon N-dimensional arrays of data elements for which a corresponding N- dimensional Scoreboard of status data is held. Hazard checking for data dependencies upon data elements within the N-dimensional array of data elements is performed by looking up the corresponding status value within the Scoreboard. The status data for a given data element within the Scoreboard is located at a position which can be derived from the position of the data elements within its N-dimensional array. Thus, a two- dimensional array of video macroblocks can have a corresponding two-dimensional Scoreboard of status data indicating whether individual macroblocks have, for example, either already been deblocked or have not already been deblocked.

Abstract translation: 描述了一种并行处理技术，用于对保持状态数据的相应的N维记分板的数据元素的N维阵列执行并行处理操作。 通过查看记分板内的相应状态值来执行数据元素N维数组内的数据元素的数据依赖性的危害检查。 记分板内的给定数据元素的状态数据位于可从其N维阵列内的数据元素的位置导出的位置。 因此，视频宏块的二维阵列可以具有相应的状态数据的二维记分板，该记分板指示各个宏块是否已经被解块或尚未被去块。

公开(公告)号：WO2008050094A1

公开(公告)日：2008-05-02

申请号：PCT/GB2007/003995

申请日：2007-10-19

Applicant: ARM LIMITED ,  REID, Alastair, David ,  FORD, Simon, Andrew ,  KNEEBONE, Katherine, Elizabeth

Inventor： REID, Alastair, David ,  FORD, Simon, Andrew ,  KNEEBONE, Katherine, Elizabeth

IPC: G06F11/36

CPC classification number: G06F11/3632 ,  G06F11/362 ,  G06F11/3636

Abstract: A diagnostic method is described for generating diagnostic data relating to processing of an instruction stream, wherein said instruction stream has been compiled from a source instruction stream to include multiple threads, said method comprising the steps of: (i) initiating a diagnostic procedure in which at least a portion of said instruction stream is executed; (ii) controlling a scheduling order for executing instructions within said at least a portion of said instruction stream to cause execution of a sequence of thread portions, said sequence being determined in response to one or more rules, at least one of said rules defining an order of execution of said thread portions to follow an order of said source instruction stream. In this way, the diagnostic method can generate a debug view of a parallelised program which is the same as, or at least similar to, a debug view which would be provided when debugging the original non-parallelised program.

Abstract translation: 描述了一种用于产生与指令流的处理有关的诊断数据的诊断方法，其中所述指令流已经从源指令流被编译以包括多个线程，所述方法包括以下步骤：（i）启动诊断过程，其中 执行所述指令流的至少一部分; （ii）控制用于执行在所述指令流的所述至少一部分内的指令的调度顺序以引起线程部分序列的执行，所述序列响应于一个或多个规则来确定，所述规则中的至少一个限定 所述线程部分的执行顺序遵循所述源指令流的顺序。 以这种方式，诊断方法可以生成与调试原始非并行化程序时将提供的调试视图相同或至少相似的并行程序的调试视图。

公开(公告)号：WO2007110557A1

公开(公告)日：2007-10-04

申请号：PCT/GB2006/001139

申请日：2006-03-29

Applicant: ARM LIMITED ,  FORD, Simon, Andrew

Inventor： FORD, Simon, Andrew

IPC: G06F12/06 ,  G06F12/08

CPC classification number: G06F12/0284 ,  G06F12/08 ,  G06F12/0831 ,  G06F2212/251 ,  G06F2212/253

Abstract: A data processing system (2) is provided including a local memory (4) and a main memory (6). The local memory (4) is accessed by a data engine (8) using local- memory physical addresses. The main memory (6) is accessed by a microprocessor (10) using main-memory addresses. A translation store (16) serves to store physical address TAGs indicating the mapping between data stored within the local memory (4) and corresponding data stored within the main memory (6). A coherency management mechanism (18) serves to use MESI coherency control data to manage the coherency between data values stored both in the local memory (4) and the main memory (6).

Abstract translation: 提供了包括本地存储器（4）和主存储器（6）的数据处理系统（2）。 本地存储器（4）由使用本地存储器物理地址的数据引擎（8）访问。 主存储器（6）由使用主存储器地址的微处理器（10）访问。 翻译存储器（16）用于存储指示存储在本地存储器（4）内的数据与存储在主存储器（6）内的对应数据之间的映射的物理地址标签。 一致性管理机制（18）用于使用MESI一致性控制数据来管理存储在本地存储器（4）和主存储器（6）中的数据值之间的一致性。

公开(公告)号：WO2006010872A1

公开(公告)日：2006-02-02

申请号：PCT/GB2004/003258

申请日：2004-07-27

Applicant: ARM LIMITED ,  FORD, Simon, Andrew ,  ROSE, Andrew, Christopher

Inventor： FORD, Simon, Andrew ,  ROSE, Andrew, Christopher

IPC: G06F9/32

CPC classification number: G06F9/30072 ,  G06F9/3001 ,  G06F9/30163

Abstract: A data processing apparatus and method of handling conditional instructions in such a data processing apparatus are provided. The data processing apparatus has a pipelined processing unit for executing instructions including at least one conditional instruction from a set of conditional instructions, and a register file having a plurality of registers operable to store data values for access by the pipelined processing unit when executing the instructions. A register specified by an instruction may be either a source register holding a source data value for that instruction or a destination register into which is stored a result data value generated by execution of that instruction. The register file has a predetermined number of read ports via which data values can be read from registers of the register file. The pipelined processing unit is operable when executing the at least one conditional instruction to produce a result data value which, dependent on the existence of the condition specified by that conditional instruction, represents either the result of the computation specified by that conditional instruction or a current data value stored in the destination register for that conditional instruction. Further, each conditional instruction in the set is constrained to specify a register that is both a source register and a destination register for that conditional instruction, thereby reducing the minimum number of read ports required to support execution of that conditional instruction by the pipelined processing unit.

Abstract translation: 提供了一种在这种数据处理装置中处理条件指令的数据处理装置和方法。 数据处理装置具有流水线处理单元，用于执行包括来自一组条件指令的至少一个条件指令的指令，以及具有多个寄存器的寄存器文件，该多个寄存器可操作以在执行指令时存储由流水线处理单元进行访问的数据值 。 由指令指定的寄存器可以是保存该指令的源数据值的源寄存器或存储通过执行该指令而生成的结果数据值的目标寄存器。 寄存器文件具有预定数量的读取端口，经由该读取端口可以从寄存器文件的寄存器读取数据值。 流水线处理单元在执行至少一个条件指令以产生结果数据值时可操作，结果数据值取决于由该条件指令指定的条件的存在表示由该条件指令指定的计算结果或当前值 存储在该条件指令的目标寄存器中的数据值。 此外，集合中的每个条件指令被限制为指定用于该条件指令的源寄存器和目的地寄存器的寄存器，从而减少支持由流水线处理单元执行该条件指令所需的读端口的最小数量 。

公开(公告)号：WO2007066058A1

公开(公告)日：2007-06-14

申请号：PCT/GB2005/004696

申请日：2005-12-06

Applicant: ARM LIMITED ,  BRADLEY, Daryl, Wayne ,  MILNE, George, James ,  HORLEY, John, Michael ,  FORD, Simon, Andrew

Inventor： BRADLEY, Daryl, Wayne ,  MILNE, George, James ,  HORLEY, John, Michael ,  FORD, Simon, Andrew

IPC: G06F1/32

CPC classification number: G06F1/3203

Abstract: A data processing apparatus and methods are disclosed. The data processing apparatus comprises: data processing elements operable to process data; an. energy management unit operable to generate energy management information indicative of an energy state of at least one of the data processing elements when processing said data; and logic operable to receive said energy management information and to generate energy management information items associating said energy state with the processing of said data. The information items can provide visibility of how the Energy State of the data processing elements vary in response to the processing of data. Providing this visibility of the Energy State can advantageously enable more detailed the energy management to be performed and the Energy State of the data processing elements to be optimized.

Abstract translation: 公开了一种数据处理装置和方法。 数据处理装置包括：可操作以处理数据的数据处理元件; 一个。 能量管理单元，用于在处理所述数据时产生指示数据处理元件中的至少一个的能量状态的能量管理信息; 以及可操作以接收所述能量管理信息并产生将所述能量状态与所述数据的处理相关联的能量管理信息项的逻辑。 信息项可以提供对数据处理元件的能量状态如何响应于数据处理而变化的可见性。 提供能量状态的这种可见性可以有利地使得能够更详细地执行能量管理并且优化数据处理元件的能量状态。

公开(公告)号：WO2010007338A3

公开(公告)日：2010-08-12

申请号：PCT/GB2009001503

申请日：2009-06-12

Applicant: ADVANCED RISC MACH LTD ,  FORD SIMON ANDREW ,  HILL STEPHEN JOHN

Inventor： FORD SIMON ANDREW ,  HILL STEPHEN JOHN

IPC: G06F11/34

CPC classification number: G06F9/3844 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/815 ,  G06F2201/875 ,  G06F2201/88 ,  G06F2201/885 ,  Y02B70/16 ,  Y02D10/34

Abstract: A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.

Abstract translation: 公开了一种数据处理装置，包括用于执行数据处理处理的处理器和用于执行调谐处理的处理器。 数据处理装置被布置为使得与数据处理过程不同的处理的调整过程可以访问数据处理过程的推测机制的参数并调整参数，使得机制不同地推测，并且以这种方式， 可以提高该数据处理过程。

公开(公告)号：WO2008050076A1

公开(公告)日：2008-05-02

申请号：PCT/GB2007/003223

申请日：2007-08-24

Applicant: ARM LIMITED ,  FORD, Simon, Andrew ,  REID, Alastair, David ,  KNEEBONE, Katherine, Elizabeth ,  GRIMLEY-EVANS, Edmund

Inventor： FORD, Simon, Andrew ,  REID, Alastair, David ,  KNEEBONE, Katherine, Elizabeth ,  GRIMLEY-EVANS, Edmund

IPC: G06F11/36

CPC classification number: G06F11/362 ,  G06F11/3636

Abstract: An asymmetric multiprocessor apparatus (2) is provided in which respective slave diagnostic units (20, 22, 24) are associated with corresponding execution mechanisms (6, 8, 10). A master, diagnostic unit (26) tracks the migration of thread execution between the different execution mechanisms (6, 8, 10) so that the execution of a given thread can be followed by the diagnostic mechanisms (20, 22, 24, 26) and this information provided to the programmer. The execution mechanisms (6, 8, 10) can be diverse such as a general purpose processor (6), a DMA unit (12), a coprocessor, an VLIW processor, a digital signal processor (8) and a hardware accelerator (10). The asymmetric multiprocessor apparatus (2) will also typically include an asymmetric memory hierarchy such as including two or more of a global memory, a shared memory (16), a private memory (18) and a cache memory (14).

Abstract translation: 提供了一种非对称多处理器装置（2），其中相应的从属诊断单元（20,22,24）与相应的执行机构（6,8,10）相关联。 主诊断单元（26）跟踪不同执行机构（6,8,10）之间的线程执行的迁移，使得给定线程的执行可以由诊断机构（20,22,24,26）跟随， 并将此信息提供给程序员。 执行机构（6,8,10）可以是多样的，例如通用处理器（6），DMA单元（12），协处理器，VLIW处理器，数字信号处理器（8）和硬件加速器（10） ）。 非对称多处理器装置（2）还通常将包括非对称存储器层级，例如包括全局存储器，共享存储器（16），专用存储器（18）和高速缓存存储器（14）中的两个或更多个。

公开(公告)号：WO2007101969A1

公开(公告)日：2007-09-13

申请号：PCT/GB2006/000795

申请日：2006-03-06

Applicant: ARM LIMITED ,  FORD, Simon, Andrew ,  GHOSH, Mrinmoy ,  ÖZER, Emre ,  BILES, Stuart, David

Inventor： FORD, Simon, Andrew ,  GHOSH, Mrinmoy ,  ÖZER, Emre ,  BILES, Stuart, David

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F2212/1016 ,  G06F2212/6032 ,  Y02D10/13

Abstract: A data processing apparatus is provided having processing logic for performing a sequence of operations, and a cache having a plurality of segments for storing data values for access by the processing logic. The processing logic is arranged, when access to a data value is required, to issue an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure during which it is determined whether the data value is stored in the cache. Indication logic is provided which, in response to an address portion of the address, provides for each of at least a subject of the segments an indication as to whether the data value is stored in that segment. The indication logic has guardian storage for storing guarding data, and hash logic for performing a hash operation on the address portion in order to reference the guarding data to determine each indication. Each indication indicates whether the data value is either definitely not stored in the associated segment or is potentially stored with the associated segment, and the cache is then operable to use the indications produced by the indication logic to affect the lookup procedure performed in respect of any segment whose associated indication indicates that the data value is definitely not stored in that segment. This technique has been found to provide a particularly power efficient mechanism for accessing the cache.

Abstract translation: 提供了具有用于执行操作序列的处理逻辑的数据处理装置，以及具有多个段的高速缓存，用于存储由处理逻辑进行访问的数据值。 当需要访问数据值时，处理逻辑被布置为发出指定与该数据值相关联的存储器中的地址的访问请求，并且高速缓存响应于地址以执行查找过程，在此期间确定是否确定是否 数据值存储在缓存中。 提供指示逻辑，响应于地址的地址部分，为段中的至少一个对象提供关于数据值是否存储在该段中的指示。 指示逻辑具有用于存储保护数据的保护存储和用于对地址部分执行散列操作的散列逻辑，以引用保护数据来确定每个指示。 每个指示指示数据值是否绝对不存储在相关联的段中或潜在地与相关联的段相关联，并且高速缓存然后可操作以使用由指示逻辑产生的指示来影响关于任何 其相关联的指示表明数据值绝对不存储在该段中。 已经发现这种技术提供了用于访问高速缓存的特别有效的机构。

公开(公告)号：WO2007099273A1

公开(公告)日：2007-09-07

申请号：PCT/GB2006/000754

申请日：2006-03-03

Applicant: ARM LIMITED ,  FORD, Simon, Andrew ,  REID, Alastair

Inventor： FORD, Simon, Andrew ,  REID, Alastair

IPC: G06F11/30

CPC classification number: G06F11/364 ,  G06F11/30

Abstract: An integrated circuit, and method of reviewing values of one or more signals occurring within that integrated circuit, are provided. The integrated circuit comprises processing logic for executing a program, and monitoring logic for reviewing values of one or more signals occurring within the integrated circuit as a result of execution of the program. The monitoring logic stores configuration data, which can be software programmed in relation to the signals to be monitored. Further, the monitoring logic makes use of a Bloom filter which, for a value to be reviewed, performs a hash operation on that value in order to reference the configuration data to determine whether that value is either definitely not a value within the range or is potentially a value within the range of values. If the value is determined to be within the set of values, then a trigger signal is generated which can be used to trigger a further monitoring process.

Abstract translation: 提供一种集成电路以及检查在该集成电路内发生的一个或多个信号的值的方法。 集成电路包括用于执行程序的处理逻辑，以及作为执行程序的结果来检查在集成电路内发生的一个或多个信号的值的监视逻辑。 监视逻辑存储配置数据，其可以相对于待监视的信号进行软件编程。 此外，监视逻辑利用布隆过滤器，对于要被检查的值，对该值进行哈希运算以引用配置数据，以确定该值是否绝对不是该范围内的值，或者是 潜在的价值范围内的值。 如果该值被确定为在该值集合内，则产生可用于触发进一步监视过程的触发信号。