公开(公告)号：WO2006114029A1

公开(公告)日：2006-11-02

申请号：PCT/CN2005/001686

申请日：2005-10-14

Applicant: 崇贸科技股份有限公司 ,  黄志丰 ,  简铎欣 ,  林振宇 ,  杨大勇

Inventor： 黄志丰 ,  简铎欣 ,  林振宇 ,  杨大勇

IPC: H01L21/76 ,  H01L27/10 ,  H01L29/786

CPC classification number: H01L27/0928 ,  H01L21/823878 ,  H01L21/823892

Abstract: A metal oxide semiconductor (MOS) field effect transistor device having isolation structure for single chip integration, wherein PMOS field effect transistor comprises: a first N-type well formed in the P-type substrate, a first P-type area formed in the first N-type well, a P+-type drain region formed in the first P-type area, a P+-type source region and a N+-type contact region form a first source electrode, the first N-type well surrounds P+-type source region and N+-type contact region of PMOSFET; NMOS field effect transistor comprises: a second N-type well formed in the P-type substrate, a second P-type area formed in the second N-type well, a N+-type drain region formed in the second N-type well, a N+-type source region and a P+-type contact region form a second source electrode, the second P-type area surrounds N+-type source region and P+-type contact region of NMOS field effect transistor, a plurality of separate P-type area are formed in P-type substrate to provide an isolation between the transistors.

公开(公告)号：WO2006116902A1

公开(公告)日：2006-11-09

申请号：PCT/CN2005/001687

申请日：2005-10-14

Applicant: 崇贸科技股份有限公司 ,  黄志丰 ,  简铎欣 ,  林振宇 ,  杨大勇

Inventor： 黄志丰 ,  简铎欣 ,  林振宇 ,  杨大勇

IPC: H01L21/76 ,  H01L27/10 ,  H01L29/786

CPC classification number: H01L29/7816 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: Provided is a metal oxide semiconductor field effect transistor device having isolation structure, wherein N-type metal oxide semiconductor field effect transistor includes a first N-type buried layer and a P-type epitaxial layer formed in the P-type substrate; P-type field effect transistor includes a second N-type buried layer and the said P-type epitaxial layer formed in the P-type substrate. The said first, second N-type buried layer and said P-type epitaxial layer provide an isolation between the field effect transistors. Moreover, a plurality of the separated P-type area are formed in P-type epitaxial layer to provide further isolative effect; there is a first interval between the first thick field oxide layer and the first P-type area so as to improve the breakdown voltage of the N-type field effect transistor; there is a second interval between the second thick field oxide layer and the second N-type well so as to improve the breakdown voltage of the P-type field effect transistor.

公开(公告)号：WO2006102805A1

公开(公告)日：2006-10-05

申请号：PCT/CN2005/001685

申请日：2005-10-14

Applicant: 崇贸科技股份有限公司 ,  黄志丰 ,  简铎欣 ,  林振宇 ,  杨大勇

Inventor： 黄志丰 ,  简铎欣 ,  林振宇 ,  杨大勇

IPC: H01L21/76 ,  H01L27/10 ,  H01L29/786

CPC classification number: H01L21/823493 ,  H01L21/823418 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: 本发明公开了一种具有隔离结构的MOS场效应晶体管，其中一N型MOS场效应晶体管包括有一第一N型阱，一包围起一第一源极区域与一第一接点区域的第一P型区域于该第一N型阱内形成，一第一漏极区域亦形成于第一N型阱内；其中一P型MOS场效应晶体管包括有一第二N型阱，一包围起一第二漏极区域的第二P型区域于该第二N型阱内形成，一第二源极区域与一第二接点区域形成于该第二N型阱内。另外，一栅极置于一薄栅氧化层与一厚场氧化层上，用以控制场效应晶体管组件通道的电流量，分离的P型区域形成于一P型基板内用以提供场效应晶体管间的隔离。此外，一第一间隙与一第二间隙可提高场效应晶体管组件的击穿电压。