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    METHODS AND APPARATUS FOR READING A FULL-SWING MEMORY ARRAY
    1.
    发明申请
    METHODS AND APPARATUS FOR READING A FULL-SWING MEMORY ARRAY 审中-公开
    读取全闪存存储阵列的方法和设备

    公开(公告)号：WO2006138150A2

    公开(公告)日：2006-12-28

    申请号：PCT/US2006022374

    申请日：2006-06-05

    Applicant: QUALCOMM INC ,  KOLLA YESHWANT N ,  BURDA GREGORY CHRISTOPHER ,  FISCHER JEFFREY HERBERT

    Inventor： KOLLA YESHWANT N ,  BURDA GREGORY CHRISTOPHER ,  FISCHER JEFFREY HERBERT

    IPC: G11C7/10

    CPC classification number: G11C7/22 ,  G11C7/18

    Abstract: Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines and a global bit line. In order to reduce power consumption, a method of driving the global bit line includes the step of coupling the plurality of local bit lines to the global bit line through a plurality of tri-state devices. The method further includes the steps of generating a global select signal to enable one of the plurality of tri-state devices and selecting a corresponding local bit line to drive the output of the enabled tri-state device. In this way, the global bit line is statically driven so that consecutive reads of bits having the same value read over the global bit line do not result in transitioning the state of the global bit line.

    Abstract translation: 公开了在读取全摆幅存储器阵列时降低功率的技术。 全摆幅存储器阵列包括多个局部位线和全局位线。 为了降低功耗，驱动全局位线的方法包括通过多个三态装置将多个局部位线耦合到全局位线的步骤。 该方法还包括以下步骤：产生全局选择信号以使多个三态装置之一能够选择相应的局部位线来驱动所启用的三态装置的输出。 以这种方式，全局位线被静态驱动，使得在全局位线上读取具有相同值的位的连续读取不会导致全局位线的状态的转变。

    POWER SAVING STATIC-BASED COMPARATOR CIRCUITS AND METHODS AND CONTENT-ADDRESSABLE MEMORY (CAM) CIRCUITS EMPLOYING SAME
    3.
    发明申请
    POWER SAVING STATIC-BASED COMPARATOR CIRCUITS AND METHODS AND CONTENT-ADDRESSABLE MEMORY (CAM) CIRCUITS EMPLOYING SAME 审中-公开
    省电基于静态的比较器电路和方法和内容可寻址存储器（CAM）使用其的电路

    公开(公告)号：WO2010085562A1

    公开(公告)日：2010-07-29

    申请号：PCT/US2010/021655

    申请日：2010-01-21

    Applicant: QUALCOMM INCORPORATED ,  BURDA, Gregory, Christopher ,  MARTZLOFF, Jason, Philip ,  KOLLA, Yeshwant, Nagaraj

    Inventor： BURDA, Gregory, Christopher ,  MARTZLOFF, Jason, Philip ,  KOLLA, Yeshwant, Nagaraj

    IPC: G11C15/04 ,  G06F12/10 ,  G06F17/30

    CPC classification number: G11C15/04 ,  G06F17/30982 ,  Y02D10/45

    Abstract: Static-based comparators (78) and methods for comparing data are disclosed. The static-based comparator (114) is configured to selectively switch at least one comparator output (110) in response to a comparison of corresponding data (96) with compare data (98), and a validity indicator (120) for the data. If the validity indicator indicates valid data, the static- based comparator switches to drive the comparator output indicating either a match or mismatch between corresponding compared data. If the validity indicator indicates invalid data, the static-based comparator provides a mismatch on the comparator output without switching the static-based comparator regardless of whether or not the data matches the compare data. In this manner, the static-based comparator does not dissipate power switching the comparator output for data marked invalid. The static- based comparator can be employed in content addressable memories (CAMs) for comparing one or more bits of tag data to corresponding bit(s) of compare data.

    Abstract translation: 公开了基于静态的比较器（78）和比较数据的方法。 基于静态的比较器（114）被配置为响应于对比数据（96）与比较数据（98）的比较以及数据的有效性指示符（120）来选择性地切换至少一个比较器输出（110）。 如果有效性指示符指示有效数据，则基于静态的比较器切换以驱动比较器输出，指示相应的比较数据之间的匹配或不匹配。 如果有效性指示符指示无效数据，则基于静态的比较器会提供比较器输出的不匹配，而不用切换基于静态的比较器，而不管数据是否与比较数据匹配。 以这种方式，基于静态的比较器不会消耗电源切换比较器输出，标记为无效数据。 基于静态的比较器可以用于内容可寻址存储器（CAM）中，用于将标签数据的一个或多个比特与比较数据的相应比特进行比较。

    WRITE-THROUGH-READ (WTR) COMPARATOR CIRCUITS, SYSTEMS, AND METHODS EMPLOYING WRITE-BACK STAGE AND USE OF SAME WITH A MULTIPLE-PORT FILE
    4.
    发明申请
    WRITE-THROUGH-READ (WTR) COMPARATOR CIRCUITS, SYSTEMS, AND METHODS EMPLOYING WRITE-BACK STAGE AND USE OF SAME WITH A MULTIPLE-PORT FILE 审中-公开
    WRITE-THROUGH-READ（WTR）比较器电路，系统和使用写回阶段的方法以及使用多个端口文件

    公开(公告)号：WO2011100352A1

    公开(公告)日：2011-08-18

    申请号：PCT/US2011/024227

    申请日：2011-02-09

    Applicant: QUALCOMM INCORPORATED ,  BURDA, Gregory Christopher ,  MCILVAINE, Michael Scott ,  NUNAMAKER, Nathan Samuel ,  KOLLA, Yeshwant Nagaraj

    Inventor： BURDA, Gregory Christopher ,  MCILVAINE, Michael Scott ,  NUNAMAKER, Nathan Samuel ,  KOLLA, Yeshwant Nagaraj

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30141 ,  G06F9/3857

    Abstract: Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.

    Abstract translation: 通读（WTR）比较器电路和相关的WTR处理和存储器系统被公开。 WTR比较器电路可以被配置为对具有一个或多个读取和写入端口的多端口文件执行WTR功能。 WTR比较器电路中的一个或多个WTR比较器被配置为将读取的索引与可以将数据写入文件中的条目的多个写入端口中的读取索引与对应于写回阶段选择的写入端口的写入索引进行比较 。 WTR比较器然后产生WTR比较器输出，指示写入索引是否与读取索引匹配以控制WTR功能。 以这种方式，WTR比较器电路可以使用比读取和写入端口组合数更少的WTR比较器。 提供较少的WTR比较器可以降低用于WTR比较器电路的半导体管芯上的功耗，成本和面积。

    METHODS AND APPARATUS FOR READING A FULL-SWING MEMORY ARRAY
    6.
    发明申请
    METHODS AND APPARATUS FOR READING A FULL-SWING MEMORY ARRAY 审中-公开

    公开(公告)号：WO2006138150A3

    公开(公告)日：2006-12-28

    申请号：PCT/US2006/022374

    申请日：2006-06-05

    Applicant: QUALCOMM INCORPORATED ,  KOLLA, Yeshwant, N. ,  BURDA, Gregory, Christopher ,  FISCHER, Jeffrey, Herbert

    Inventor： KOLLA, Yeshwant, N. ,  BURDA, Gregory, Christopher ,  FISCHER, Jeffrey, Herbert

    IPC: G11C7/10

    Abstract: Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines and a global bit line. In order to reduce power consumption, a method of driving the global bit line includes the step of coupling the plurality of local bit lines to the global bit line through a plurality of tri-state devices. The method further includes the steps of generating a global select signal to enable one of the plurality of tri-state devices and selecting a corresponding local bit line to drive the output of the enabled tri-state device. In this way, the global bit line is statically driven so that consecutive reads of bits having the same value read over the global bit line do not result in transitioning the state of the global bit line.

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