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    INSTRUCTION PREFETCH MECHANISM
    2.
    发明申请
    INSTRUCTION PREFETCH MECHANISM 审中-公开
    指导性机制

    公开(公告)号：WO2006084288A3

    公开(公告)日：2007-01-11

    申请号：PCT/US2006006993

    申请日：2006-02-03

    Applicant: QUALCOMM INC ,  SARTORIUS THOMAS ANDREW ,  AUGSBURG VICTOR ROBERT ,  DIEFFENDERFER JAMES NORRIS ,  BRIDGES JEFFREY TODD ,  MCILVAINE MICHAEL SCOTT ,  SMITH RODNEY WAYNE

    Inventor： SARTORIUS THOMAS ANDREW ,  AUGSBURG VICTOR ROBERT ,  DIEFFENDERFER JAMES NORRIS ,  BRIDGES JEFFREY TODD ,  MCILVAINE MICHAEL SCOTT ,  SMITH RODNEY WAYNE

    IPC: G06F9/38

    CPC classification number: G06F9/3844 ,  G06F9/3804

    Abstract: A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

    Abstract translation: 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

    SEGMENTED PIPELINE FLUSHING FOR MISPREDICTED BRANCHES
    3.
    发明申请
    SEGMENTED PIPELINE FLUSHING FOR MISPREDICTED BRANCHES 审中-公开
    用于错误分支的SEGMENTED管道冲洗

    公开(公告)号：WO2008092045A1

    公开(公告)日：2008-07-31

    申请号：PCT/US2008/051966

    申请日：2008-01-24

    Applicant: QUALCOMM Incorporated ,  MCILVAINE, Michael Scott ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

    Inventor： MCILVAINE, Michael Scott ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/384 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3867

    Abstract: A processor pipeline is segmented into an upper portion - prior to instructions going out of program order - and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.

    Abstract translation: 处理器管线被分割成上部，在指令超出程序顺序之前，以及超出上部的一个或多个下部。 在检测到分支指令被错误预测时，上级流水线被刷新，从而使得从正确的分支目标地址获取指令的延迟最小化。 较低的管道可以继续执行，直到错误的分支指令确认，此时所有未提交的指令都从较低的管道冲洗。 可以通过添加错误的分支标识符来减少冲洗下层管道的复杂性和硬件成本，来利用现有的异常流水线冲洗机制。

    WRITE-THROUGH-READ (WTR) COMPARATOR CIRCUITS, SYSTEMS, AND METHODS EMPLOYING WRITE-BACK STAGE AND USE OF SAME WITH A MULTIPLE-PORT FILE
    6.
    发明申请
    WRITE-THROUGH-READ (WTR) COMPARATOR CIRCUITS, SYSTEMS, AND METHODS EMPLOYING WRITE-BACK STAGE AND USE OF SAME WITH A MULTIPLE-PORT FILE 审中-公开
    WRITE-THROUGH-READ（WTR）比较器电路，系统和使用写回阶段的方法以及使用多个端口文件

    公开(公告)号：WO2011100352A1

    公开(公告)日：2011-08-18

    申请号：PCT/US2011/024227

    申请日：2011-02-09

    Applicant: QUALCOMM INCORPORATED ,  BURDA, Gregory Christopher ,  MCILVAINE, Michael Scott ,  NUNAMAKER, Nathan Samuel ,  KOLLA, Yeshwant Nagaraj

    Inventor： BURDA, Gregory Christopher ,  MCILVAINE, Michael Scott ,  NUNAMAKER, Nathan Samuel ,  KOLLA, Yeshwant Nagaraj

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30141 ,  G06F9/3857

    Abstract: Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.

    Abstract translation: 通读（WTR）比较器电路和相关的WTR处理和存储器系统被公开。 WTR比较器电路可以被配置为对具有一个或多个读取和写入端口的多端口文件执行WTR功能。 WTR比较器电路中的一个或多个WTR比较器被配置为将读取的索引与可以将数据写入文件中的条目的多个写入端口中的读取索引与对应于写回阶段选择的写入端口的写入索引进行比较 。 WTR比较器然后产生WTR比较器输出，指示写入索引是否与读取索引匹配以控制WTR功能。 以这种方式，WTR比较器电路可以使用比读取和写入端口组合数更少的WTR比较器。 提供较少的WTR比较器可以降低用于WTR比较器电路的半导体管芯上的功耗，成本和面积。

    EFFICIENT INTERRUPT RETURN ADDRESS SAVE MECHANISM
    7.
    发明申请
    EFFICIENT INTERRUPT RETURN ADDRESS SAVE MECHANISM 审中-公开
    有效的中断返回地址保存机制

    公开(公告)号：WO2008014287A1

    公开(公告)日：2008-01-31

    申请号：PCT/US2007/074263

    申请日：2007-07-24

    Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  MCILVAINE, Michael Scott

    Inventor： SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  MCILVAINE, Michael Scott

    IPC: G06F9/32 ,  G06F9/38 ,  G06F9/42 ,  G06F9/46 ,  G06F9/48

    CPC classification number: G06F9/30054 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/3836

    Abstract: A system, apparatus and method for efficiently processing interrupts using general purpose registers in a pipelined processor. In accordance with the present disclosure, a register file may be updated to efficiently save an interrupt return address. When an interrupt request is received by the system's processor, or when the request is issued in the execution of a program, a pseudo-instruction is generated. This pseudo-instruction travels down the pipeline in the same way as other instructions and updates the register file by causing the register file to be written with the return address of the last instruction for which processing has not been completed.

    Abstract translation: 一种用于在流水线处理器中使用通用寄存器来有效地处理中断的系统，装置和方法。 根据本公开，可以更新寄存器文件以有效地保存中断返回地址。 当系统的处理器接收到中断请求时，或者当执行程序发出请求时，产生伪指令。 该伪指令以与其他指令相同的方式沿着流水线行进，并通过使用寄存器文件写入尚未完成处理的最后一条指令的返回地址来更新寄存器文件。

    METHOD AND APPARATUS FOR MANAGING INSTRUCTION FLUSHING IN A MICROPROCESSOR'S INSTRUCTION PIPELINE
    8.
    发明申请
    METHOD AND APPARATUS FOR MANAGING INSTRUCTION FLUSHING IN A MICROPROCESSOR'S INSTRUCTION PIPELINE 审中-公开
    用于管理微处理器指令管道中的指导性冲洗的方法和装置

    公开(公告)号：WO2006135590A3

    公开(公告)日：2007-05-31

    申请号：PCT/US2006021617

    申请日：2006-06-02

    Applicant: QUALCOMM INC ,  MCILVAINE MICHAEL SCOTT ,  DIEFFENDERFER JAMES NORRIS ,  SARTORIUS THOMAS ANDREW

    Inventor： MCILVAINE MICHAEL SCOTT ,  DIEFFENDERFER JAMES NORRIS ,  SARTORIUS THOMAS ANDREW

    IPC: G06F9/44

    CPC classification number: G06F9/3861 ,  G06F9/30072 ,  G06F9/3867 ,  G06F12/0855 ,  G06F12/0862 ,  G06F2212/6028

    Abstract: In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such that those instructions marked as being dependent on the branch instruction associated with the branch misprediction are flushed. Thus, the one or more circuits may be configured to mark instructions fetched into the processor's instruction pipeline(s) to indicate their branch prediction dependencies, directly or indirectly detect incorrect branch predictions, and directly or indirectly flush instructions in the instruction pipeline(s) that are marked as being dependent on an incorrect branch prediction.

    Abstract translation: 在一个或多个实施例中，处理器包括一个或多个电路，用于响应于检测到分支错误预测而选择性地从指令流水线中刷新指令，使得标记为依赖于与分支错误预测相关联的分支指令的那些指令被刷新 。 因此，一个或多个电路可以被配置为标记被提取到处理器的指令流水线中以指示其分支预测依赖性的指令，直接或间接地检测不正确的分支预测，以及直接或间接地刷新指令流水线中的指令， 这被标记为依赖于不正确的分支预测。

    REGISTER-BASED SHIFTS FOR A UNIDIRECTIONAL ROTATOR
    10.
    发明申请
    REGISTER-BASED SHIFTS FOR A UNIDIRECTIONAL ROTATOR 审中-公开
    基于注册码的移动轮转换器

    公开(公告)号：WO2007090174A1

    公开(公告)日：2007-08-09

    申请号：PCT/US2007/061414

    申请日：2007-01-31

    Applicant: QUALCOMM INCORPORATED ,  MANADATH, Abdulhameed A. ,  KLEIN, Anthony D. ,  MCILVAINE, Michael Scott

    Inventor： MANADATH, Abdulhameed A. ,  KLEIN, Anthony D. ,  MCILVAINE, Michael Scott

    IPC: G06F9/302 ,  G06F9/308 ,  G06F9/315

    CPC classification number: G06F9/30032 ,  G06F9/3001

    Abstract: A processor having a unidirectional rotator configured to shift or rotate data in one direction is disclosed. The processor also includes a control unit having logic configured to modify a shift value specified by a registered-based shift, or rotate, instruction in an opposite direction, the modified shift value being usable by the rotator to shift, or rotate, the data in the one direction, and thereby, generate the same result as if the data in the rotator had otherwise been shifted, or rotated, in the opposite direction by the shift value originally specified by the registered-based instruction. The control unit is further configured to bypass the logic and provide to the rotator a shift value specified by a register-based instruction to shift, or rotate, the data in the one direction.

    Abstract translation: 公开了一种具有单向旋转器的处理器，其被配置成在一个方向上移动或旋转数据。 处理器还包括具有逻辑的控制单元，该逻辑被配置为修改由相对方向上的基于注册的移位或旋转指令指定的移位值，修改的移位值可由旋转器使用以移动或旋转数据 一个方向，从而产生相同的结果，就好像转动器中的数据以原来由基于注册的指令最初指定的移位值以相反的方向被移位或旋转。 控制单元还被配置为绕过逻辑并向旋转器提供由基于寄存器的指令指定的移位值，以便在一个方向上移动或旋转数据。

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