公开(公告)号：WO2004002050A1

公开(公告)日：2003-12-31

申请号：PCT/US2003/019016

申请日：2003-06-13

Applicant: THOMSON LICENSING S.A. ,  CHRISTENSEN, Carl ,  WALKER, Marc, Stuart ,  BLAIR, David, Kim ,  BYTHEWAY, David, Lynn ,  ARBUCKLE, Lynn, Howard

Inventor： CHRISTENSEN, Carl ,  WALKER, Marc, Stuart ,  BLAIR, David, Kim ,  BYTHEWAY, David, Lynn ,  ARBUCKLE, Lynn, Howard

IPC: H04L1/20

CPC classification number: H04L1/22 ,  H04L1/0061 ,  H04L12/1868 ,  H04L45/60 ,  H04L49/201 ,  H04L49/206 ,  H04L49/557

Abstract: A fault-tolerant router (100) includes first and second router matrix card (122a and 122b). The first and second router matrix cards (122a, 122b) receive a common set of 4n parity encoded input digital audio data streams and respectively generates therefrom, first and second sets of M output digital audio streams. As the first and second sets of data streams propagate along the first and second router matrix cards (122a and 122b), respectively, one or more health bits are set whenever an error or other type of fault condition is detected. First and second parity check circuits (130a and 130b) are configured to detect parity errors and/or assess the relative health of the first and second sets of data streams and one of the two sets of data streams is selected as the output of the fault-tolerant router (100) based upon either the parity error analysis, health analysis or both.

Abstract translation: 容错路由器（100）包括第一和第二路由器矩阵卡（122a和122b）。 第一和第二路由器矩阵卡（122a，122b）接收4n个奇偶校验编码的输入数字音频数据流的公共组，并且分别从其生成第一和第二组M个输出数字音频流。 当第一和第二组数据流分别沿着第一和第二路由器矩阵卡（122a和122b）传播时，每当检测到错误或其它类型的故障状况时，就设置一个或多个健康位。 第一和第二奇偶校验电路（130a和130b）被配置为检测奇偶校验错误和/或评估第一和第二组数据流的相对健康状况，并且选择两组数据流中的一组作为故障的输出 基于奇偶校验错误分析，健康分析或两者兼容的不允许路由器（100）。

公开(公告)号：WO2006009605A1

公开(公告)日：2006-01-26

申请号：PCT/US2005/019115

申请日：2005-06-01

Applicant: THOMSON LICENSING S.A. ,  CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn ,  ARBUCKLE, Lynn, Howard ,  REDONDO, Randall, Geovanny

Inventor： CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn ,  ARBUCKLE, Lynn, Howard ,  REDONDO, Randall, Geovanny

IPC: H04J3/06

CPC classification number: H04J3/0688

Abstract: A router (100), for routing at least one input signal to at least one output, comprises at least one input module (4021-402x) and at least one output module (4041-404y). Each of the input and output modules includes at least one clock selector circuit (5001-500n) for selecting from among a first and second clock signal, and an oscillator signal, as a common output clock signal for the at least first router, based in part on whether at least one of the first and second clock signals has toggled. The clock selector circuit provides redundancy as well as distribution of clock signals among elements within each module.

Abstract translation: 用于将至少一个输入信号路由到至少一个输出的路由器（100）包括至少一个输入模块（4021-402x）和至少一个输出模块（4041-404y）。 每个输入和输出模块包括至少一个用于从第一和第二时钟信号中选择的时钟选择器电路（5001-500n）和作为至少第一路由器的公共输出时钟信号的振荡器信号，其基于 部分是关于第一和第二时钟信号中的至少一个是否已经切换。 时钟选择器电路在每个模块内的元件之间提供冗余以及时钟信号的分配。

公开(公告)号：WO2004002060A1

公开(公告)日：2003-12-31

申请号：PCT/US2003/019392

申请日：2003-06-20

Applicant: THOMSON LICENSING S.A. ,  CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn ,  ARBUCKLE, Lynn, Howard

Inventor： CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn ,  ARBUCKLE, Lynn, Howard

IPC: H04L12/16

CPC classification number: H04L49/90 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/901 ,  H04L49/9047

Abstract: A linearly expandable audio data router (102) comprising a routing engine (144) and a data store (134) coupled to the routing engine (144) and configured to store an input digital audio data signal received thereby as a series of data frames in a series of timeslots in response to queries of the data frames performed at a rate exceeding a maximum sample rate of the input digital audio data signal.

Abstract translation: 一种线性扩展音频数据路由器（102），包括路由引擎（144）和耦合到路由引擎（144）的数据存储（134），并被配置为将由此接收的输入数字音频数据信号作为一系列数据帧存储 响应于以超过输入数字音频数据信号的最大采样率的速率执行的数据帧的查询的一系列时隙。

公开(公告)号：WO2004002041A2

公开(公告)日：2003-12-31

申请号：PCT/US0319390

申请日：2003-06-20

Applicant: THOMSON LICENSING SA ,  CHRISTENSEN CARL ,  BYTHEWAY DAVID LYNN ,  ARBUCKLE LYNN HOWARD

Inventor： CHRISTENSEN CARL ,  BYTHEWAY DAVID LYNN ,  ARBUCKLE LYNN HOWARD

IPC: G10L19/22 ,  H04H60/04 ,  H04L

CPC classification number: G10L19/22

Abstract: An average bit time (406) and an excess sample count (406) are determined for a selected N-bit frame of AES serialized output digital audio data (404) to be encoded. An N-bit bi-phase encoded frame is then constructed (412, 414) from the N-bit frame of digital audio data, the average bit time, the excess sample count and a selected bit sampling rate (401) for the digital audio data stream. If the excess sample count is determined to be equal to zero (410), each data bit of the encoded frame would have the same time duration and thus contain the same number of samples therein (412). If the excess sample count is determined to be greater than zero (410), X bits of the encoded frame would have a time duration greater and thus contain a greater number of samples than that of the remaining N-X bits of the encoded frame (414).

Abstract translation: 对于要编码的AES串行化输出数字音频数据（404）的所选N位帧，确定平均位时间（406）和多余采样计数（406）。 然后，从数字音频数据的N位帧，平均位时间，多余采样计数和用于数字音频的选择位采样率（401）构造N位双相编码帧（412,414） 数据流。 如果多余的采样计数被确定为等于零（410），则编码帧的每个数据位将具有相同的持续时间，因此在其中包含相同数目的样本（412）。 如果多余的采样计数被确定为大于零（410），编码帧的X位将具有更长的持续时间，并且因此包含比编码帧（414）的其余NX位的采样数更多的采样数， 。

公开(公告)号：WO2004002089A1

公开(公告)日：2003-12-31

申请号：PCT/US2003/019114

申请日：2003-06-17

Applicant: THOMSON LICENSING S.A. ,  CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn

Inventor： CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn

IPC: H04L12/56

CPC classification number: H04J3/0688 ,  H04J3/0685 ,  H04L45/28 ,  H04L45/583 ,  H04L45/60 ,  H04M3/12 ,  H04M2201/14 ,  H04Q3/521 ,  H04Q2213/13003 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13167 ,  H04Q2213/13214 ,  H04Q2213/13242 ,  H04Q2213/1334 ,  H04Q2213/13341

Abstract: Supportably mounted by each chassis (102c, 104c) of a multi-chassis broadcast router (100) are primary router matrix cards (102a, 104a), redundant router matrix cards (102b, 104b) and clock-demanding input and output cards (136-1 through 136-N and 138-1 through 138-M, 142-1 through 142-N and 144-1 through 144-M). A first master clock (134) resides on the primary router matrix card (102a) of a first chassis (102c) while a second master clock (154) resides on the redundant router matrix card (104b) of a second chassis (104c). Each master clock (134, 154) is configured to provide a respective common clock signal to all of the input and output cards (136-1 through 136-N and 138-1 through 138-M, 142-1 through 142-N and 144-1 through 144-M) of the first and second chassis (102c and 104c). Control logic (148, 156) determines whether the first master clock (134) or the second master clock (154) issues the common clock signal.

Abstract translation: 主机路由器矩阵卡（102a，104a），冗余路由器矩阵卡（102b，104b）和需要时钟要求的输入和输出卡（136）的每个机架（102c，104c）可支撑地安装 -1至136-N和138-1至138-M，142-1至142-N和144-1至144-M）。 第一主时钟（134）驻留在第一机箱（102c）的主路由器矩阵卡（102a）上，而第二主时钟（154）驻留在第二机箱（104c）的冗余路由器矩阵卡（104b）上。 每个主时钟（134,154）被配置为向所有输入和输出卡（136-1至136-N和138-1至138-M，142-1至142-N）提供相应的公共时钟信号，并且 144-1至144-M）的第一和第二底盘（102c和104c）。 控制逻辑（148,156）确定第一主时钟（134）或第二主时钟（154）是否发出公共时钟信号。

公开(公告)号：WO2004002041A3

公开(公告)日：2003-12-31

申请号：PCT/US2003/019390

申请日：2003-06-20

Applicant: THOMSON LICENSING S.A. ,  CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn ,  ARBUCKLE, Lynn, Howard

Inventor： CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn ,  ARBUCKLE, Lynn, Howard

IPC: H04L27/00

Abstract: An average bit time (406) and an excess sample count (406) are determined for a selected N-bit frame of AES serialized output digital audio data (404) to be encoded. An N-bit bi-phase encoded frame is then constructed (412, 414) from the N-bit frame of digital audio data, the average bit time, the excess sample count and a selected bit sampling rate (401) for the digital audio data stream. If the excess sample count is determined to be equal to zero (410), each data bit of the encoded frame would have the same time duration and thus contain the same number of samples therein (412). If the excess sample count is determined to be greater than zero (410), X bits of the encoded frame would have a time duration greater and thus contain a greater number of samples than that of the remaining N-X bits of the encoded frame (414).

公开(公告)号：WO2013033247A1

公开(公告)日：2013-03-07

申请号：PCT/US2012/052906

申请日：2012-08-29

Applicant: CONTROL4 CORPORATION ,  RUSSELL, James K. ,  BYTHEWAY, David Lynn ,  SCHONLE, William Richard

Inventor： RUSSELL, James K. ,  BYTHEWAY, David Lynn ,  SCHONLE, William Richard

IPC: H02J1/08

CPC classification number: H02J3/14 ,  G01R21/006 ,  H02J2003/143 ,  Y02B70/3225 ,  Y02B70/3266 ,  Y04S20/222 ,  Y04S20/242

Abstract: An electronic device for managing energy is described. The electronic device includes a voltage sensor module that monitors a voltage waveform. The voltage sensor module includes discrete components. The electronic device includes a current sensor module that monitors a current waveform. The current sensor module includes discrete components. The electronic device is coupled to the voltage sensor module and to the current sensor module. The computing module determines a phase margin based on the voltage waveform and the current waveform. The electronic device includes a control module coupled to the computing module. The control module controls a load based on the voltage waveform, current waveform and phase margin. The control module includes discrete components. The voltage sensor module, the current sensor module, the computing module and the control module are housed within a wall box.

Abstract translation: 描述了用于管理能量的电子设备。 电子设备包括监测电压波形的电压传感器模块。 电压传感器模块包括分立元件。 电子设备包括监视电流波形的电流传感器模块。 电流传感器模块包括分立元件。 电子设备耦合到电压传感器模块和电流传感器模块。 计算模块根据电压波形和电流波形确定相位裕度。 电子设备包括耦合到计算模块的控制模块。 控制模块根据电压波形，电流波形和相位裕度控制负载。 控制模块包括分立元件。 电压传感器模块，电流传感器模块，计算模块和控制模块被容纳在墙箱内。

公开(公告)号：WO2004002080A1

公开(公告)日：2003-12-31

申请号：PCT/US2003/018821

申请日：2003-06-13

Applicant: THOMSON LICENSING S.A. ,  CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn ,  HAYDEN, Mitchell, T.

Inventor： CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn ,  HAYDEN, Mitchell, T.

IPC: H04L12/54

CPC classification number: H04L45/16 ,  H04L45/00 ,  H04L45/583 ,  H04L45/60 ,  H04L49/15 ,  H04L49/201 ,  H04L49/203 ,  H04L49/205 ,  H04L49/206 ,  H04L49/25 ,  H04L49/30 ,  H04L49/45 ,  H04L49/552 ,  H04L2012/5664

Abstract: A fully redundant linearly expandable router (100) is comprised of first, second, third and fourth router components (102, 104, 106 and 108). Each router component (102, 104, 106 and 108) includes first and second routing engines (144 and 152, 178 and 186, 212 and 220, and 246 and 254). First, second and third discrete links (110, 112 and 114) couple the first routing engine (144) to the first routing engines (178, 212 and 246), respectively. Fourth and fifth discrete links (116 and 118) couple the first routing engine (178) to the first routing engines (212 and 246), respectively. A sixth discrete link (120) couples the routing engine (212) to the routing engine (246). Seventh, eighth and ninth discrete links (122, 124 and 126) couple the second routing engine (152) to the second routing engines (186, 220 and 254), respectively. Tenth and eleventh discrete links (128 and 130) couple the second routing engine (186) to the second routing engines (220 and 254), respectively. A twelfth discrete link (132) couples the routing engine (220) to the router engine (254).

Abstract translation: 完全冗余的线性可扩展路由器（100）由第一，第二，第三和第四路由器组件（102,104,106和108）组成。 每个路由器组件（102,104,106和108）包括第一和第二路由引擎（144和152,178以及186,212和220以及246和254）。 首先，第二和第三离散链路（110,112和114）分别将第一路由引擎（144）耦合到第一路由引擎（178,212和246）。 第四和第五离散链路（116和118）分别将第一路由引擎（178）耦合到第一路由引擎（212和246）。 第六离散链路（120）将路由引擎（212）耦合到路由引擎（246）。 第七，第八和第九离散链接（122,124和126）分别将第二路由引擎（152）耦合到第二路由引擎（186,220和254）。 第十和第十一离散链接（128和130）分别将第二路由引擎（186）耦合到第二路由引擎（220和254）。 第十二离散链路（132）将路由引擎（220）耦合到路由器引擎（254）。

公开(公告)号：WO2004002072A1

公开(公告)日：2003-12-31

申请号：PCT/US2003/018848

申请日：2003-06-16

Applicant: THOMSON LICENSING S.A. ,  CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn ,  HAYDEN, Mitchell, T.

Inventor： CHRISTENSEN, Carl ,  BYTHEWAY, David, Lynn ,  HAYDEN, Mitchell, T.

IPC: H04L12/28

CPC classification number: H04L45/586 ,  H04L12/54 ,  H04L45/00 ,  H04L45/16

Abstract: A linearly expandable router (100) is comprised of first, second, third and fourth router components (102, 104, 106 and 108). First, second and third discrete links (110, 112 and 114) couple an input side of a routing engine (128) of the first router component (102) to an input side of a routing engine (128) of the second, third and fourth router components (104, 106 and 108). Similarly, fourth and fifth discrete links (116 and 118) couple the input side of the routing engine (128) for the second router component (104) to the input side of the routing engine (128) of the third and fourth router components (106 and 108), respectively. Finally, a sixth discrete link (120) couples the input side of the routing engine (128) for the third router component (106) to the input side of the router engine (128) for the fourth router component (108).

Abstract translation: 线性扩展路由器（100）由第一，第二，第三和第四路由器组件（102,104,106和108）组成。 首先，第二和第三离散链路（110,112和114）将第一路由器组件（102）的路由引擎（128）的输入侧耦合到第二，第三和第三离散链路的路由引擎（128）的输入侧， 第四路由器组件（104,106和108）。 类似地，第四和第五离散链路（116和118）将用于第二路由器组件（104）的路由引擎（128）的输入侧耦合到第三和第四路由器组件（122）的路由引擎（128）的输入侧 106和108）。 最后，第六离散链路（120）将用于第三路由器组件（106）的路由引擎（128）的输入侧耦合到用于第四路由器组件（108）的路由器引擎（128）的输入侧。