ASYMMETRIC PICTURE COMPRESSION
    2.
    发明申请
    ASYMMETRIC PICTURE COMPRESSION 审中-公开
    不对称图片压缩

    公开(公告)号:WO1991019384A1

    公开(公告)日:1991-12-12

    申请号:PCT/US1991003733

    申请日:1991-05-29

    Abstract: A wide screen television apparatus comprises a video display (244) having a first format display ratio of width to height, for example approximately 16x9. A first video signal defines a first picture. A second video signal defines a second picture in a second format display ratio of width to height smaller than the first format display ratio, for example approximately 4x3. A video signal processor (301) asymmetrically compresses the second picture, for example 4:1 horizontally and 3:1 vertically. A video memory (420) stores lines of video of the asymmetrically compressed picture. Another video signal processor (300) combines portions of lines of video in the first video signal with the stored lines of video of the asymmetrically compressed picture for simultaneous display of the first and second pictures. The asymmetrically compressed second picture is displayed without aspect ratio distortion. The second picture can form an inset within the first picture. A single picture display can itself comprise a full screen of pictures from one source or from multiple sources.

    Abstract translation: 宽屏幕电视设备包括具有宽度与高度的第一格式显示比例的视频显示器(244),例如大约16×9。 第一视频信号定义第一图像。 第二视频信号以比第一格式显示比例小的宽度与高度的第二格式显示比定义第二图像,例如大约4×3。 视频信号处理器(301)不对称地压缩第二图像,例如水平地为4:1,垂直地为3:1。 视频存储器(420)存储不对称压缩图像的视频行。 另一个视频信号处理器(300)将第一视频信号中的视频行的部分与存储的非对称压缩图像的视频行组合,用于同时显示第一和第二图像。 显示不对称压缩的第二图像,而不显示纵横比失真。 第二张照片可以在第一张照片中形成一个插图。 单个图像显示器本身可以包括来自一个源或多个源的全屏图像。

    WIDE SCREEN TELEVISION
    4.
    发明申请
    WIDE SCREEN TELEVISION 审中-公开
    大屏幕电视

    公开(公告)号:WO1991019388A1

    公开(公告)日:1991-12-12

    申请号:PCT/US1991003740

    申请日:1991-05-29

    Abstract: A video display has a first format display ratio. A mapping circuit maps an adjustable picture display area on the video display. A signal processor generates first and second video signals from input video signals having one of different format display ratios. A switching circuit selectively couples video signal sources as the input video signals. The signal processor can manipulate data from the input video signals by selective interpolation and cropping. A synchronizing circuit synchronizes the first and second signal processors with the mapping circuit. A selecting circuit selects as an output video signal between one of the first and second processed video signals and a combination of the first and second processed video signals. A control circuit controls the mapping circuit, the first and second signal processors and the selecting circuit to adjust in format display ratio and image aspect ratio each picture represented in the output video signal. One of the different format display ratios of the input video signals can be the same as the first format display ratio of the video display. The mapping circuit can comprise a raster generating circuit for a cathode ray tube or an address matrix generator for a liquid crystal display.

    Abstract translation: 视频显示具有第一格式显示比率。 映射电路映射视频显示器上的可调节图像显示区域。 信号处理器从具有不同格式显示比率的输入视频信号产生第一和第二视频信号。 开关电路选择性地将视频信号源耦合为输入视频信号。 信号处理器可以通过选择性插值和裁剪来处理来自输入视频信号的数据。 同步电路使第一和第二信号处理器与映射电路同步。 选择电路选择第一和第二处理视频信号之一之间的输出视频信号以及第一和第二处理视频信号的组合。 控制电路控制映射电路,第一和第二信号处理器和选择电路,以在输出视频信号中表示的每个图像的格式显示比和图像宽高比进行调整。 输入视频信号的不同格式显示比之一可以与视频显示的第一格式显示比相同。 映射电路可以包括用于阴极射线管的光栅产生电路或用于液晶显示器的地址矩阵发生器。

    FIELD SYNCHRONIZATION SYSTEM WITH WRITE/READ POINTER CONTROL
    5.
    发明申请
    FIELD SYNCHRONIZATION SYSTEM WITH WRITE/READ POINTER CONTROL 审中-公开
    具有写/读指针控制的现场同步系统

    公开(公告)号:WO1991019379A1

    公开(公告)日:1991-12-12

    申请号:PCT/US1991003745

    申请日:1991-05-29

    Abstract: A field synchronization system for asynchronous video signals, comprises a video display synchronized with a first video signal having a first line rate component and a first field rate component. A second video signal having a second line rate component is first stored in a field memory, having synchronous write and read ports. The second video signal is thereafter speeded up in a multiple line memory (354) having asynchronous write and read ports and independently resettable write and read pointers. The second video signal may be subsampled, written and read into and out of the field memory respectively and written into the multiple line memory, all synchronously with the second line rate component. The second video signal is read out of the multiple line memory (354) synchronously with the first line rate component. The write pointer is reset by a circuit (320) which samples the first field rate component with the second line rate component. The read pointer is reset by a circuit which samples the first field rate component with the first line rate component.

    Abstract translation: 用于异步视频信号的场同步系统包括与具有第一线速率分量和第一场速率分量的第一视频信号同步的视频显示。 具有第二线速率分量的第二视频信号首先存储在具有同步写和读端口的场存储器中。 此后,第二视频信号在具有异步写和读端口的多行存储器(354)中被加速并且具有独立可复位的写和读指针。 第二视频信号可以分别被采样,写入和读出场存储器,并且与第二线速率分量同步地写入多行存储器。 与第一线速率分量同步地从多行存储器(354)读出第二视频信号。 写指针由电路(320)复位,电路(320)用第二线速率分量对第一场速率分量进行采样。 读指针由利用第一线速率分量对第一场速率分量进行采样的电路复位。

    FIELD SYNCHRONIZATION SYSTEM MAINTAINING INTERLACE INTEGRITY
    8.
    发明申请
    FIELD SYNCHRONIZATION SYSTEM MAINTAINING INTERLACE INTEGRITY 审中-公开
    维护内部完整性的现场同步系统

    公开(公告)号:WO1991019385A1

    公开(公告)日:1991-12-12

    申请号:PCT/US1991003741

    申请日:1991-05-29

    Abstract: First and second field type detectors (702, 710) for first and second video signals have outputs indicating whether the video signals have first or second field types. The first video signal is synchronized with the second video signal for a combined display by a synchronous field memory (350) and an asynchronous multiple line memory (354). The field type of the second video signal is changed when necessary to match the field type of the first video signal to maintain interlace integrity in the combined display. A field type changing circuit (712, 714, 718) which controls the synchronizing, has a first mode of operation which delays writing a current field of the first field type by one horizontal line period, a second mode of operation which advances writing a current field of the second field type by one horizontal line period and a third mode of operation which maintains a current field type. A plurality of selectable interlace correction signals are generated, each being appropriate for one of the plurality of comparison outcomes.

    Abstract translation: 用于第一和第二视频信号的第一和第二场型检测器(702,710)具有指示视频信号是否具有第一或第二场类型的输出。 第一视频信号与第二视频信号同步,用于通过同步场存储器(350)和异步多行存储器(354)的组合显示。 当需要匹配第一视频信号的场类型以维持组合显示中的交错完整性时,改变第二视频信号的场类型。 控制同步的场型改变电路(712,714,718)具有第一操作模式,该第一操作模式延迟将第一场类型的当前场写入一个水平行周期;第二操作模式, 第二场类型的场和一个水平行周期的第三操作模式和保持当前场类型的第三操作模式。 产生多个可选择的交错校正信号,每个可选择的交错校正信号适合于多个比较结果之一。

    APPARATUS AND METHOD FOR ENCODING AND DECODING SIGNALS
    10.
    发明申请
    APPARATUS AND METHOD FOR ENCODING AND DECODING SIGNALS 审中-公开
    用于编码和解码信号的装置和方法

    公开(公告)号:WO2009051687A3

    公开(公告)日:2010-01-21

    申请号:PCT/US2008011705

    申请日:2008-10-14

    Abstract: New capabilities will allow conventional broadcast transmission to be available to mobile devices. The present embodiments describe an apparatus and method for encoding and decoding signals. A method (1100) includes the steps of generating (1110) data blocks, encoding (1140) a first set of data blocks using a first encoding rate, encoding (1140) a second set of data blocks using a second encoding rate, and generating (1180) a control packet, the control packet identifying the first set of data blocks and the first encoding rate, and identifying the second set of data blocks and the second encoding rate. An apparatus (1200) includes a first decoder (1216) receiving data and decoding a first subset of the data, including a control packet, at a first decoding rate and a controller (1260) controlling the operation of the first decoder (1216) based on the decoded control packet.

    Abstract translation: 新功能将允许传统的广播传输可用于移动设备。 本实施例描述了用于对信号进行编码和解码的装置和方法。 一种方法(1100)包括以下步骤:使用第一编码速率产生(1110)数据块,对第一组数据块进行编码(1140),使用第二编码速率编码(1140)第二组数据块,并产生 (1180)控制分组,所述控制分组识别所述第一组数据块和所述第一编码速率,以及识别所述第二组数据块和所述第二编码速率。 一种设备(1200)包括:第一解码器(1216),以第一解码速率接收数据并解码数据的第一子集(包括控制分组);以及控制器(1260),其基于第一解码器(1216)的操作来控制 在解码的控制包上。

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