公开(公告)号：WO2004068707A3

公开(公告)日：2004-08-12

申请号：PCT/US2004/002311

申请日：2004-01-27

Applicant: SUN MICROSYSTEMS, INC. ,  DURHAM, Christopher, M. ,  LAUV, Hang, B. ,  GOLLA, Robert, T.

Inventor： DURHAM, Christopher, M. ,  LAUV, Hang, B. ,  GOLLA, Robert, T.

IPC: H03K3/037

Abstract: A high-speed, noise-safe, non-inverting flip-flop is provided. In the flip-flop, a buffer (103) is used to isolate a data input terminal (101) from the remainder of the flip-flop circuitry to prevent erroneous operation of the flip-flop circuitry. Also, a slave node (slave) is connected to a master node (master) to avoid the need for an additional buffer on a data signal critical path, thus preserving the high-speed of the flip-flop circuitry. Overlapped clock signals are used to control data signal transmission to the master node (master) and the slave node (slave). The overlapped clock signals allow the buffer (103) used to isolate the data input terminal (101) to also be used to drive the data signal through the master node (master) to the slave node (slave).

公开(公告)号：WO2004068707A2

公开(公告)日：2004-08-12

申请号：PCT/US2004002311

申请日：2004-01-27

Applicant: SUN MICROSYSTEMS INC ,  DURHAM CHRISTOPHER M ,  LAUV HANG B ,  GOLLA ROBERT T

Inventor： DURHAM CHRISTOPHER M ,  LAUV HANG B ,  GOLLA ROBERT T

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/012

Abstract: A high-speed, noise-safe, non-inverting flip-flop is provided. In the flip-flop, a buffer (103) is used to isolate a data input terminal (101) from the remainder of the flip-flop circuitry to prevent erroneous operation of the flip-flop circuitry. Also, a slave node (slave) is connected to a master node (master) to avoid the need for an additional buffer on a data signal critical path, thus preserving the high-speed of the flip-flop circuitry. Overlapped clock signals are used to control data signal transmission to the master node (master) and the slave node (slave). The overlapped clock signals allow the buffer (103) used to isolate the data input terminal (101) to also be used to drive the data signal through the master node (master) to the slave node (slave).

Abstract translation: 提供高速，噪声安全，非反相触发器。 在触发器中，使用缓冲器（103）来隔离触发器电路的其余部分的数据输入端（101）以防止触发器电路的错误操作。 此外，从节点（从属）连接到主节点（主节点），以避免在数据信号关键路径上需要附加缓冲器，从而保持触发器电路的高速。 重叠时钟信号用于控制数据信号传输到主节点（主节点）和从节点（从节点）。 重叠的时钟信号允许用于隔离数据输入端（101）的缓冲器（103）也用于通过主节点（主机）向从节点（从）驱动数据信号。