公开(公告)号：WO2006005025A3

公开(公告)日：2007-01-25

申请号：PCT/US2005023647

申请日：2005-06-30

Applicant: SUN MICROSYSTEMS INC ,  GOLLA ROBERT T ,  BROOKS JEFFREY S ,  OLSON CHRISTOPHER H

Inventor： GOLLA ROBERT T ,  BROOKS JEFFREY S ,  OLSON CHRISTOPHER H

IPC: G06F9/38 ,  G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/3851 ,  Y02D10/128 ,  Y02D10/171

Abstract: A method and apparatus for controlling power consumption in a multi-threaded processor. In one embodiment, the processor includes at least one logic unit for processing instructions. The logic unit includes a plurality of positions, wherein each of the plurality of positions corresponds to at least one instruction thread. Clock signals may be provided to the logic unit via a clock gating unit. The clock gating unit is configured to inhibit a clock signal from being provided to a corresponding one of the thread positions when no instruction thread is active for that position. The inhibiting of the clock signal for an inactive thread position may reduce power consumption by the processor.

Abstract translation: 一种用于控制多线程处理器中的功耗的方法和装置。 在一个实施例中，处理器包括用于处理指令的至少一个逻辑单元。 逻辑单元包括多个位置，其中多个位置中的每一个对应于至少一个指令线程。 时钟信号可以经由时钟门控单元提供给逻辑单元。 时钟门控单元被配置为当没有指令线程对于该位置有效时，禁止将时钟信号提供给相应的一个线程位置。 禁止线程位置的时钟信号的抑制可能会降低处理器的功耗。

公开(公告)号：WO2006004830A3

公开(公告)日：2006-10-26

申请号：PCT/US2005023094

申请日：2005-06-30

Applicant: SUN MICROSYSTEMS INC ,  GOLLA ROBERT T

Inventor： GOLLA ROBERT T

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3861

Abstract: In one embodiment, a multithreaded processor includes a plurality of buffers, each configured to store instructions corresponding to a respective thread. The multithreaded processor also includes a pick unit coupled to the plurality of buffers. The pick unit may pick from at least one of the buffers in a given cycle, a valid instruction based upon a thread selection algorithm. The pick unit may further cancel, in the given cycle, the picking of the valid instruction in response to receiving a cancel indication.

Abstract translation: 在一个实施例中，多线程处理器包括多个缓冲器，每个缓冲器被配置为存储对应于相应线程的指令。 多线程处理器还包括耦合到多个缓冲器的拾取单元。 拾取单元可以在给定周期中从至少一个缓冲器中选择基于线程选择算法的有效指令。 拾取单元可以在给定的周期中进一步取消响应于接收到取消指示而选择有效指令。

公开(公告)号：WO2006004830A2

公开(公告)日：2006-01-12

申请号：PCT/US2005/023094

申请日：2005-06-30

Applicant: SUN MICROSYSTEMS, INC. ,  GOLLA, Robert, T.

Inventor： GOLLA, Robert, T.

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3861

Abstract: In one embodiment, a multithreaded processor includes a plurality of buffers, each configured to store instructions corresponding to a respective thread. The multithreaded processor also includes a pick unit coupled to the plurality of buffers. The pick unit may pick from at least one of the buffers in a given cycle, a valid instruction based upon a thread selection algorithm. The pick unit may further cancel, in the given cycle, the picking of the valid instruction in response to receiving a cancel indication.

Abstract translation: 在一个实施例中，多线程处理器包括多个缓冲器，每个缓冲器被配置为存储对应于相应线程的指令。 多线程处理器还包括耦合到多个缓冲器的拾取单元。 挑选单元可以在给定周期中从至少一个缓冲器中选择基于线程选择算法的有效指令。 拾取单元可以在给定的周期中进一步取消响应于接收到取消指示而选择的有效指令。

公开(公告)号：WO2006004975A1

公开(公告)日：2006-01-12

申请号：PCT/US2005/023415

申请日：2005-06-30

Applicant: SUN MICROSYSTEMS, INC. ,  GOLLA, Robert, T. ,  HETHERINGTON, Ricky, C.

Inventor： GOLLA, Robert, T. ,  HETHERINGTON, Ricky, C.

IPC: G06F1/32

CPC classification number: G06F9/3869 ,  G06F1/32 ,  G06F1/3203 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3891

Abstract: A method and apparatus for controlling power consumption in a processor. In one embodiment, a processor includes a pipeline. The pipeline includes logic for fetching instructions, issuing instructions, and executing instructions. The processor also includes a power management unit. The power management unit is configured to input M stalls into the pipeline every N instruction cycles (where M and N are integer value and wherein M is less than N).

Abstract translation: 一种用于控制处理器中的功率消耗的方法和装置。 在一个实施例中，处理器包括流水线。 流水线包括用于获取指令，发出指令和执行指令的逻辑。 处理器还包括电源管理单元。 电源管理单元被配置为每N个指令周期（其中M和N是整数值，并且其中M小于N）将M个时序输入流水线。

公开(公告)号：WO2006005025A2

公开(公告)日：2006-01-12

申请号：PCT/US2005/023647

申请日：2005-06-30

Applicant: SUN MICROSYSTEMS, INC. ,  GOLLA, Robert, T. ,  BROOKS, Jeffrey, S. ,  OLSON, Christopher, H.

Inventor： GOLLA, Robert, T. ,  BROOKS, Jeffrey, S. ,  OLSON, Christopher, H.

IPC: G06F9/38

CPC classification number: G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/3851 ,  Y02D10/128 ,  Y02D10/171

Abstract: A method and apparatus for controlling power consumption in a multi-threaded processor. In one embodiment, the processor includes at least one logic unit for processing instructions. The logic unit includes a plurality of positions, wherein each of the plurality of positions corresponds to at least one instruction thread. Clock signals may be provided to the logic unit via a clock gating unit. The clock gating unit is configured to inhibit a clock signal from being provided to a corresponding one of the thread positions when no instruction thread is active for that position. The inhibiting of the clock signal for an inactive thread position may reduce power consumption by the processor.

Abstract translation: 一种用于控制多线程处理器中的功耗的方法和装置。 在一个实施例中，处理器包括用于处理指令的至少一个逻辑单元。 逻辑单元包括多个位置，其中多个位置中的每一个对应于至少一个指令线程。 时钟信号可以经由时钟门控单元提供给逻辑单元。 时钟门控单元被配置为当没有指令线程对于该位置有效时，禁止将时钟信号提供给相应的一个线程位置。 禁止线程位置的时钟信号可能会降低处理器的功耗。

公开(公告)号：WO2006004826A3

公开(公告)日：2006-01-12

申请号：PCT/US2005/023077

申请日：2005-06-30

Applicant: SUN MICROSYSTEMS, INC. ,  HETHERINGTON, Ricky, C. ,  GROHOSKI, Gregory, F. ,  GOLLA, Robert, T.

Inventor： HETHERINGTON, Ricky, C. ,  GROHOSKI, Gregory, F. ,  GOLLA, Robert, T.

IPC: G06F9/46 ,  G06F9/30

Abstract: An apparatus and method for fine-grained multithreading in a multipipelined processor core. According to one embodiment, a processor may include instruction fetch logic configured to assign a given one of a plurality of threads to a corresponding one of a plurality of thread groups, where each of the plurality of thread groups may comprise a subset of the plurality of threads, to issue a first instruction from one of the plurality of threads during one execution cycle, and to issue a second instruction from another one of the plurality of threads during a successive execution cycle. The processor may further include a plurality of execution units, each configured to execute instructions issued from a respective thread group.

公开(公告)号：WO2006004826A2

公开(公告)日：2006-01-12

申请号：PCT/US2005023077

申请日：2005-06-30

Applicant: SUN MICROSYSTEMS INC ,  HETHERINGTON RICKY C ,  GROHOSKI GREGORY F ,  GOLLA ROBERT T

Inventor： HETHERINGTON RICKY C ,  GROHOSKI GREGORY F ,  GOLLA ROBERT T

IPC: G06F9/00

CPC classification number: G06F9/3851 ,  G06F9/3885 ,  G06F12/0842 ,  G06F12/0859

Abstract: An apparatus and method for fine-grained multithreading in a multipipelined processor core. According to one embodiment, a processor may include instruction fetch logic configured to assign a given one of a plurality of threads to a corresponding one of a plurality of thread groups, where each of the plurality of thread groups may comprise a subset of the plurality of threads, to issue a first instruction from one of the plurality of threads during one execution cycle, and to issue a second instruction from another one of the plurality of threads during a successive execution cycle. The processor may further include a plurality of execution units, each configured to execute instructions issued from a respective thread group.

Abstract translation: 用于多分支处理器核心中的细粒度多线程的设备和方法。 根据一个实施例，处理器可以包括指令提取逻辑，其被配置为将多个线程中给定的一个线程分配给多个线程组中的相应一个线程组，其中多个线程组中的每一个可以包括多个线程组中的子集 线程在一个执行周期期间从多个线程中的一个线程发出第一指令，并且在连续执行周期期间从多个线程中的另一个发出第二指令。 处理器还可以包括多个执行单元，每个执行单元被配置为执行从相应线程组发出的指令。

公开(公告)号：WO2004068707A3

公开(公告)日：2004-08-12

申请号：PCT/US2004/002311

申请日：2004-01-27

Applicant: SUN MICROSYSTEMS, INC. ,  DURHAM, Christopher, M. ,  LAUV, Hang, B. ,  GOLLA, Robert, T.

Inventor： DURHAM, Christopher, M. ,  LAUV, Hang, B. ,  GOLLA, Robert, T.

IPC: H03K3/037

Abstract: A high-speed, noise-safe, non-inverting flip-flop is provided. In the flip-flop, a buffer (103) is used to isolate a data input terminal (101) from the remainder of the flip-flop circuitry to prevent erroneous operation of the flip-flop circuitry. Also, a slave node (slave) is connected to a master node (master) to avoid the need for an additional buffer on a data signal critical path, thus preserving the high-speed of the flip-flop circuitry. Overlapped clock signals are used to control data signal transmission to the master node (master) and the slave node (slave). The overlapped clock signals allow the buffer (103) used to isolate the data input terminal (101) to also be used to drive the data signal through the master node (master) to the slave node (slave).

公开(公告)号：WO2004068707A2

公开(公告)日：2004-08-12

申请号：PCT/US2004002311

申请日：2004-01-27

Applicant: SUN MICROSYSTEMS INC ,  DURHAM CHRISTOPHER M ,  LAUV HANG B ,  GOLLA ROBERT T

Inventor： DURHAM CHRISTOPHER M ,  LAUV HANG B ,  GOLLA ROBERT T

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/012

Abstract: A high-speed, noise-safe, non-inverting flip-flop is provided. In the flip-flop, a buffer (103) is used to isolate a data input terminal (101) from the remainder of the flip-flop circuitry to prevent erroneous operation of the flip-flop circuitry. Also, a slave node (slave) is connected to a master node (master) to avoid the need for an additional buffer on a data signal critical path, thus preserving the high-speed of the flip-flop circuitry. Overlapped clock signals are used to control data signal transmission to the master node (master) and the slave node (slave). The overlapped clock signals allow the buffer (103) used to isolate the data input terminal (101) to also be used to drive the data signal through the master node (master) to the slave node (slave).

Abstract translation: 提供高速，噪声安全，非反相触发器。 在触发器中，使用缓冲器（103）来隔离触发器电路的其余部分的数据输入端（101）以防止触发器电路的错误操作。 此外，从节点（从属）连接到主节点（主节点），以避免在数据信号关键路径上需要附加缓冲器，从而保持触发器电路的高速。 重叠时钟信号用于控制数据信号传输到主节点（主节点）和从节点（从节点）。 重叠的时钟信号允许用于隔离数据输入端（101）的缓冲器（103）也用于通过主节点（主机）向从节点（从）驱动数据信号。