公开(公告)号：WO2022171299A1

公开(公告)日：2022-08-18

申请号：PCT/EP2021/053510

申请日：2021-02-12

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  GABOR, Ron

Inventor： YANOVER, Igor ,  SADE, Raanan ,  BERGER, Yair ,  ZHOU, Yongbin ,  LI, Shuo ,  FU, Qiang ,  LI, Kai

IPC: G06F12/0846 ,  G06F12/0864 ,  G06F12/14 ,  G06F21/44

Abstract: A system including a logic component for memory management and a method for mitigation of security vulnerabilities, resulting from memory accesses offending memory allocation rules is disclosed. Pointers exceeding their allocated range are comparatively common bugs of software written in low-level languages such as assembly, C or C++. Memory allocation offending memory accesses may also be deliberate features of malware. The disclosure provided a low performance overhead method of mitigating the vulnerability type by registering indications of the context requesting a memory access, referred to as context identifiers. The indications are based on properties such as privilege level, EL, program counter value, linear address, physical address, and/or the like. When a context submits a memory accesses offending memory allocation rules it is marked as an offending context. When the offending context issues a following memory access, it may be aborted using an exception, interrupt, or a trap, minimizing the vulnerability window and the effect on other processes.

公开(公告)号：WO2010056511A2

公开(公告)日：2010-05-20

申请号：PCT/US2009062219

申请日：2009-10-27

Applicant: INTEL CORP ,  OUZIEL IDO ,  RAPPOPORT LIHU ,  VALENTINE ROBERT ,  GABOR RON ,  RAGHUVANSHI PANKAJ

Inventor： OUZIEL IDO ,  RAPPOPORT LIHU ,  VALENTINE ROBERT ,  GABOR RON ,  RAGHUVANSHI PANKAJ

IPC: G06F9/06 ,  G06F9/22 ,  G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/30196 ,  G06F9/3836 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/4063 ,  G06F2212/452 ,  G06F2212/62 ,  Y02B60/1228 ,  Y02B60/1235 ,  Y02D10/14 ,  Y02D10/151

Abstract: A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

Abstract translation: 一种在计算机系统内实现高效指令融合的技术。 在一个实施例中，如果指令队列内的第一指令与第二指令可融合，则处理器逻辑将第二指令的处理延迟阈值时间量。

公开(公告)号：WO2012087561A3

公开(公告)日：2012-08-16

申请号：PCT/US2011063466

申请日：2011-12-06

Applicant: INTEL CORP ,  SAGER DAVID J ,  SASANKA RUCHIRA ,  GABOR RON ,  RAIKIN SHLOMO ,  NUZMAN JOSEPH ,  PELED LEEOR ,  DOMER JASON A ,  KIM HO-SEOP ,  WU YOUFENG ,  YAMADA KOICHI ,  NGAI TIN-FOOK ,  CHEN HOWARD H ,  BOBBA JAYARAM ,  COOK JEFFREY J ,  SHAIKH OSMAR M ,  SRINIVAS SURESH

Inventor： SAGER DAVID J ,  SASANKA RUCHIRA ,  GABOR RON ,  RAIKIN SHLOMO ,  NUZMAN JOSEPH ,  PELED LEEOR ,  DOMER JASON A ,  KIM HO-SEOP ,  WU YOUFENG ,  YAMADA KOICHI ,  NGAI TIN-FOOK ,  CHEN HOWARD H ,  BOBBA JAYARAM ,  COOK JEFFREY J ,  SHAIKH OSMAR M ,  SRINIVAS SURESH

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F8/4442 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/54 ,  G06F11/3612 ,  G06F11/3636 ,  G06F11/3648 ,  G06F2213/0038

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Abstract translation: 描述了用于将程序自动分解成多个并行线程的硬件和软件系统的系统，设备和方法。 在一些实施例中，系统和设备执行原始代码分解和/或生成的线程执行的方法。

公开(公告)号：WO2010056511A3

公开(公告)日：2010-05-20

申请号：PCT/US2009/062219

申请日：2009-10-27

Applicant: INTEL CORPORATION ,  OUZIEL, Ido ,  RAPPOPORT, Lihu ,  VALENTINE, Robert ,  GABOR, Ron ,  RAGHUVANSHI, Pankaj

Inventor： OUZIEL, Ido ,  RAPPOPORT, Lihu ,  VALENTINE, Robert ,  GABOR, Ron ,  RAGHUVANSHI, Pankaj

IPC: G06F9/06 ,  G06F9/22 ,  G06F9/30

Abstract: A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

公开(公告)号：WO2010053837A3

公开(公告)日：2010-05-14

申请号：PCT/US2009/062736

申请日：2009-10-30

Applicant: INTEL CORPORATION ,  FALIK, Ohad ,  RAPPOPORT, Lihu ,  GABOR, Ron ,  KUROLAP, Yulia ,  MISHAELI, Michael

Inventor： FALIK, Ohad ,  RAPPOPORT, Lihu ,  GABOR, Ron ,  KUROLAP, Yulia ,  MISHAELI, Michael

IPC: G06F9/06 ,  G06F9/30

Abstract: In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.

公开(公告)号：WO2010053837A2

公开(公告)日：2010-05-14

申请号：PCT/US2009062736

申请日：2009-10-30

Applicant: INTEL CORP ,  FALIK OHAD ,  RAPPOPORT LIHU ,  GABOR RON ,  KUROLAP YULIA ,  MISHAELI MICHAEL

Inventor： FALIK OHAD ,  RAPPOPORT LIHU ,  GABOR RON ,  KUROLAP YULIA ,  MISHAELI MICHAEL

IPC: G06F9/06 ,  G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/3855 ,  G06F9/3857

Abstract: In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一个指令解码器，其可以接收输入指令和路径选择信号，并且响应于路径选择信号将输入指令解码为第一指令代码或第二指令代码。 代表相同输入指令的两个不同的指令代码可以被执行单元用于执行针对不同数据长度优化的操作。 描述和要求保护其他实施例。

公开(公告)号：WO2007040793A1

公开(公告)日：2007-04-12

申请号：PCT/US2006/030183

申请日：2006-08-03

Applicant: INTEL CORPORATION ,  GABOR, Ron ,  LEIBOWITZ, Nathaniel ,  TSADIK, Meir ,  KULBAK, Yoram

Inventor： GABOR, Ron ,  LEIBOWITZ, Nathaniel ,  TSADIK, Meir ,  KULBAK, Yoram

IPC: G06F17/50

CPC classification number: G06F11/3457 ,  G06F17/5022

Abstract: An embodiment of the present invention is a technique to simulate performance of a multi-core system. A micro-architecture effect is estimated from each core in the multi-core system. A model of a memory hierarchy associated with each core is simulated. The simulated model of the memory hierarchy is superpositioned on the estimated micro-architecture effect to produce a performance figure for the multi-core system.

Abstract translation: 本发明的一个实施例是一种模拟多核系统性能的技术。 从多核系统中的每个核心估计微架构效应。 模拟与每个核心相关联的内存层次的模型。 存储器层次的模拟模型叠加在估计的微架构效应上，以产生多核系统的性能指标。

公开(公告)号：WO2012087561A2

公开(公告)日：2012-06-28

申请号：PCT/US2011/063466

申请日：2011-12-06

Applicant: INTEL CORPORATION ,  SAGER, David J. ,  SASANKA, Ruchira ,  GABOR, Ron ,  RAIKIN, Shlomo ,  NUZMAN, Joseph ,  PELED, Leeor ,  DOMER, Jason A. ,  KIM, Ho-Seop ,  WU, Youfeng ,  YAMADA, Koichi ,  NGAI, Tin-Fook ,  CHEN, Howard H. ,  BOBBA, Jayaram ,  COOK, Jeffrey J. ,  SHAIKH, Osmar M. ,  SRINIVAS, Suresh

Inventor： SAGER, David J. ,  SASANKA, Ruchira ,  GABOR, Ron ,  RAIKIN, Shlomo ,  NUZMAN, Joseph ,  PELED, Leeor ,  DOMER, Jason A. ,  KIM, Ho-Seop ,  WU, Youfeng ,  YAMADA, Koichi ,  NGAI, Tin-Fook ,  CHEN, Howard H. ,  BOBBA, Jayaram ,  COOK, Jeffrey J. ,  SHAIKH, Osmar M. ,  SRINIVAS, Suresh

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F8/4442 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/54 ,  G06F11/3612 ,  G06F11/3636 ,  G06F11/3648 ,  G06F2213/0038

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Abstract translation: 描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。 在一些实施例中，系统和装置执行原始代码分解和/或生成的线程执行的方法。

公开(公告)号：WO2007038011A1

公开(公告)日：2007-04-05

申请号：PCT/US2006/035961

申请日：2006-09-12

Applicant: INTEL CORPORATION ,  KULBAK, Yoram ,  SHAMIA, Doron ,  RAYNOR, Scott ,  HELD, Jim ,  GABOR, Ron

Inventor： KULBAK, Yoram ,  SHAMIA, Doron ,  RAYNOR, Scott ,  HELD, Jim ,  GABOR, Ron

IPC: G06F9/46

CPC classification number: G06F9/4843

Abstract: An embodiment of the present invention is a technique to provide a real-time threading service to an application in a multi-core environment. An executive is launched, within a most privilege level of an operating system (OS), on a real-time core in the multi- core environment. The real-time core is sequestered from the OS. A real-time thread is created in a least privilege level on the real-time core for an application using a library. The library is loaded by the application. The real-time thread shares a virtual address space with the application.

Abstract translation: 本发明的实施例是一种向多核环境中的应用提供实时线程服务的技术。 在多核环境中的实时核心上，一个执行者在操作系统（OS）的最特权级别中启动。 实时核心是从操作系统中隔离出来的。 在使用库的应用程序的实时内核的最小权限级别中创建实时线程。 该库由应用程序加载。 实时线程与应用程序共享虚拟地址空间。