公开(公告)号：WO2018164762A1

公开(公告)日：2018-09-13

申请号：PCT/US2018/012077

申请日：2018-01-02

Applicant: QUALCOMM INCORPORATED

Inventor： SAMADI, Kambiz ,  ANSARI, Amin ,  DU, Yang

IPC: G06F15/76 ,  H01L21/822 ,  H01L25/065 ,  H01L27/06

CPC classification number: G06F15/80 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/384 ,  G06F9/3867 ,  G06F12/0875 ,  G06F15/76 ,  G06F15/803 ,  G06F2212/452 ,  H01L21/8221 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores ("cores") to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC. Because 3DICs can overlap different IC tiers and/or align similar components in the same IC tier, the cores can be designed and located between or within different IC tiers in a 3DIC to reduce communication distance associated with processor core communication to share workload and/or resources, thus improving performance of the multi-processor CPU design.

公开(公告)号：WO2018125384A1

公开(公告)日：2018-07-05

申请号：PCT/US2017/060432

申请日：2017-11-07

Applicant: INTEL CORPORATION

Inventor： KANTECKI, Tomasz ,  FRIEDMAN, Ben-Zion ,  MCDONNELL, Niall D. ,  RICHARDSON, Bruce

IPC: G06F12/0802

CPC classification number: G06F13/4282 ,  G06F12/0875 ,  G06F13/126 ,  G06F13/4022 ,  G06F2212/452 ,  G06F2213/0026

Abstract: Examples include techniques for coalescing doorbells in a request message. Example techniques include gathering doorbells to access a device. The gathered are combined in a cache line structure and the cache line structure is written to a cache or buffer for a central processing unit in a single write operation.

公开(公告)号：WO2018063582A1

公开(公告)日：2018-04-05

申请号：PCT/US2017/047793

申请日：2017-08-21

Applicant: INTEL CORPORATION

Inventor： WALD, Ingo

IPC: G06T15/06 ,  G06T1/20

CPC classification number: G06T15/06 ,  G06F12/0875 ,  G06F2212/452 ,  G06T1/20 ,  G06T1/60 ,  G06T2210/21

Abstract: An apparatus and method are described for performing a distance test in a ray tracing system. For example, one embodiment of a graphics processing apparatus comprises: a ray tracing traversal/intersection unit to identify two or more ray-surface intersections, each of the ray-surface intersections being assigned a unique hit point identifier (ID); and a distance testing module to disambiguate the order of the ray-surface intersections using the hit point ID if the two or more of the ray-surface intersections share the same distance.

Abstract translation: 描述了用于在射线追踪系统中执行距离测试的装置和方法。 例如，图形处理设备的一个实施例包括：光线追踪遍历/相交单元，用于标识两个或更多个光线表面交叉点，每个光线表面交叉点被分配唯一的命中点标识符（ID）; 以及距离测试模块，如果所述两个或更多个射线表面交叉点共享相同的距离，则使用所述命中点ID消除所述射线表面相交的顺序。

公开(公告)号：WO2017106101A3

公开(公告)日：2017-08-10

申请号：PCT/US2016066188

申请日：2016-12-12

Applicant: CHARLES STARK DRAPER LABORATORY INC

Inventor： DEHON ANDRE' ,  BOLING ELI

IPC: G06F21/52 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F21/62

CPC classification number: G06F12/0875 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/3867 ,  G06F12/1408 ,  G06F12/1458 ,  G06F15/78 ,  G06F21/52 ,  G06F21/6218 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452

Abstract: Techniques are described for metadata processing that can be used to encode an arbitrary number of security policies for code running on a processor. Metadata may be added to every word in the system and a metadata processing unit may be used that works in parallel with data flow to enforce an arbitrary set of policies. In one aspect, the metadata may be characterized as unbounded and software programmable to be applicable to a wide range of metadata processing policies. Techniques and policies have a wide range of uses including, for example, safety, security, and synchronization. Additionally, described are aspects and techniques in connection with metadata processing in an embodiment based on the RISC-V architecture.

Abstract translation: 描述了用于元数据处理的技术，其可以用于对处理器上运行的代码编码任意数量的安全策略。 元数据可以被添加到系统中的每个单词中，并且可以使用元数据处理单元，其与数据流并行地执行任意一组策略。 在一个方面，元数据可以被表征为无界的并且软件可编程以适用于广泛范围的元数据处理策略。 技术和策略具有广泛的用途，例如包括安全性，安全性和同步性。 另外，在基于RISC-V架构的实施例中描述了与元数据处理相关的方面和技术。

公开(公告)号：WO2017112190A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/062913

申请日：2016-11-18

Applicant: INTEL CORPORATION

Inventor： OULD-AHMED-VALL, Elmoustapha ,  ASTAFEV, Nikita

IPC: G06F9/30 ,  G06F12/084

CPC classification number: G06F9/30036 ,  G06F9/30101 ,  G06F9/3016 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/452

Abstract: A processor includes a front end to decode an instruction, a temporary destination, and an allocator to assign the instruction to an execution unit to execute the instruction to get a selected column of data into a destination register. The execution unit includes an element counter, a logic to determine an index from an index vector based on the element count, a logic to compute an address of the data, a row to be loaded into the temporary destination, and a data processing unit to copy a portion of the temporary destination into the element of the destination register.

Abstract translation: 处理器包括解码指令的前端，临时目的地和分配器，以将该指令分配给执行单元以执行指令以将选定的数据列取到目的地寄存器。 执行单元包括元素计数器，基于元素计数从索引向量确定索引的逻辑，计算数据的地址的逻辑，要加载到临时目的地的行，以及数据处理单元到 将临时目标的一部分复制到目标寄存器的元素中。

公开(公告)号：WO2017112171A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/062688

申请日：2016-11-18

Applicant: INTEL CORPORATION

Inventor： GOKHALE, Indraneil M. ,  OULD-AHMED-VALL, Elmoustapha ,  YOUNT, Charles R. ,  VALLES, Antonio C.

IPC: G06F9/38 ,  G06F12/0862 ,  G06F15/80

CPC classification number: G06F9/30029 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3016 ,  G06F9/345 ,  G06F9/3555 ,  G06F9/3802 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/6028

Abstract: A processor includes an execution unit to execute instructions to load indices from an array of indices, optionally perform scatters, and prefetch (to a specified cache) contents of target locations for future scatters from arbitrary locations in memory. The execution unit includes logic to load, for each target location of a scatter or prefetch operation, an index value to be used in computing the address in memory for the operation. The index value may be retrieved from an array of indices identified for the instruction. The execution unit includes logic to compute the addresses based on the sum of a base address specified for the instruction, the index value retrieved for the location, and a prefetch offset (for prefetch operations), with optional scaling. The execution unit includes logic to retrieve data elements from contiguous locations in a source vector register specified for the instruction to be scattered to the memory.

Abstract translation: 处理器包括执行单元以执行指令以从指数阵列加载指数，可选地执行散射，并且从目标位置的内容预取（到特定高速缓冲存储器）用于未来分散的内容从存储器中的任意位置 。 执行单元包括用于为分散或预取操作的每个目标位置加载要用于计算存储器中用于该操作的地址的索引值的逻辑。 索引值可以从为该指令识别的索引数组中检索。 执行单元包括用于基于为指令指定的基地址，为位置检索的索引值和预取偏移量（用于预取操作）的总和来计算地址的逻辑，以及可选的缩放。 执行单元包括从源向量寄存器中的连续位置检索数据元素的逻辑，所述源向量寄存器被指定为分散到存储器的指令。

公开(公告)号：WO2017074612A1

公开(公告)日：2017-05-04

申请号：PCT/US2016/053060

申请日：2016-09-22

Applicant: INTEL CORPORATION

Inventor： KUMAR, Karthik ,  DIMITROV, Martin P.

IPC: G06F9/30 ,  G06F12/0862

CPC classification number: G06F9/30047 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/20 ,  G06F2212/452

Abstract: In one embodiment, a processor includes a core having a fetch logic to fetch instructions, a decode logic to decode a first persistent memory prefetch instruction and provide the decoded first persistent memory prefetch instruction to a control logic. In turn, the control logic is to enable prefetch of data requested by the first persistent memory prefetch instruction and storage of the data in a location external to the processor. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括具有用于提取指令的提取逻辑的核心，用于解码第一持久存储器预取指令并将经解码的第一持久存储器预取指令提供给控制逻辑的解码逻辑。 进而，控制逻辑能够预取第一持久性存储器预取指令所请求的数据并将数据存储在处理器外部的位置中。 描述并要求保护其他实施例。

公开(公告)号：WO2017048659A1

公开(公告)日：2017-03-23

申请号：PCT/US2016/051420

申请日：2016-09-13

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： BURGER, Douglas C.

IPC: G06F12/0806 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Technology related to prefetching instruction blocks is disclosed. In one example of the disclosed technology, a processor comprises a block-based processor core for executing a program comprising a plurality of instruction blocks. The block-based processor core can include prefetch logic and a local buffer. The prefetch logic can be configured to receive a reference to a predicted instruction block and to determine a mapping of the predicted instruction block to one or more lines. The local buffer can be configured to selectively store portions of the predicted instruction block and to provide the stored portions of the predicted instruction block when control of the program passes along a predicted execution path to the predicted instruction block.

Abstract translation: 公开了与预取指令块有关的技术。 在所公开技术的一个示例中，处理器包括用于执行包括多个指令块的程序的基于块的处理器核心。 基于块的处理器核心可以包括预取逻辑和本地缓冲器。 预取逻辑可以被配置为接收对预测指令块的引用，并且确定预测指令块与一行或多行的映射。 本地缓冲器可以被配置为选择性地存储预测指令块的部分，并且当程序的控制沿着预测执行路径传递到预测指令块时，提供预测指令块的存储部分。

公开(公告)号：WO2017048658A1

公开(公告)日：2017-03-23

申请号：PCT/US2016/051419

申请日：2016-09-13

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC: G06F12/0862 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Technology related to prefetching data associated with predicated stores of programs in block-based processor architectures is disclosed. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising a plurality of instructions. The block-based processor core includes decode logic and prefetch logic. The decode logic is configured to detect a predicated store instruction of the instruction block. The prefetch logic is configured to calculate a target address of the predicated store instruction and initiate a memory operation associated with the calculated target address before a predicate of the predicated store instruction is calculated.

Abstract translation: 公开了与在基于块的处理器架构中预测与节目的存储相关联的数据相关的技术。 在所公开的技术的一个示例中，处理器包括用于执行包括多个指令的指令块的基于块的处理器核心。 基于块的处理器核心包括解码逻辑和预取逻辑。 解码逻辑被配置为检测指令块的预测存储指令。 预取逻辑被配置为计算预测存储指令的目标地址，并且在计算预测存储指令的谓词之前发起与计算出的目标地址相关联的存储器操作。

公开(公告)号：WO2017048654A1

公开(公告)日：2017-03-23

申请号：PCT/US2016/051415

申请日：2016-09-13

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC: G06F12/0806 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for controlling instruction flow in block-based processor architectures. In one example of the disclosed technology, an instruction block address register stores an index address to a memory storing a plurality of instructions for an instruction block, the indexed address being inaccessible when the processor is in one or more unprivileged operational modes, one or more execution units configured to execute instructions for the instruction block, and a control unit configured to fetch and decode two or more of the plurality of instructions from the memory based on the indexed address.

Abstract translation: 公开了用于控制基于块的处理器架构中的指令流的装置和方法。 在所公开的技术的一个示例中，指令块地址寄存器将索引地址存储到存储指令块的多个指令的存储器中，当处理器处于一个或多个非特权操作模式时，索引地址是不可访问的，一个或多个 执行单元，被配置为执行指令块的指令;以及控制单元，被配置为基于索引地址从存储器中获取和解码多个指令中的两个或更多个指令。