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公开(公告)号：WO2013101232A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068242
申请日：2011-12-30
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL SAN ANDRIAN, Jesus , SAIR, Suleyman , TOLL, Bret L. , SPERBER, Zeev , GRADSTEIN, Amit , RUBENSTEIN, Asaf
Inventor： OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL SAN ANDRIAN, Jesus , SAIR, Suleyman , TOLL, Bret L. , SPERBER, Zeev , GRADSTEIN, Amit , RUBENSTEIN, Asaf
CPC classification number: G06F9/30032 , G06F9/30036
Abstract: A method of an aspect includes receiving a masked packed rotate instruction. The instruction indicates a first source packed data including a plurality of packed data elements, a packed data operation mask having a plurality of mask elements, at least one rotation amount, and a destination storage location. A result packed data is stored in the destination storage location in response to the instruction. The result packed data includes result data elements that each correspond to a different one of the mask elements in a corresponding relative position. Result data elements that are not masked out by the corresponding mask element include one of the data elements of the first source packed data in a corresponding position that has been rotated. Result data elements that are masked out by the corresponding mask element include a masked out value. Other methods, apparatus, systems, and instructions are disclosed.
Abstract translation: 一种方面的方法包括接收掩蔽的包装旋转指令。 指示指示包括多个打包数据元素的第一源打包数据，具有多个掩码元素的打包数据操作掩码，至少一个旋转量和目的地存储位置。 响应于该指令，结果打包数据被存储在目的地存储位置。 结果打包数据包括每个对应于相应相对位置中的不同掩模元素的结果数据元素。 未被相应的掩码元素掩蔽的结果数据元素包括在已旋转的对应位置中的第一源打包数据的数据元素中的一个。 由相应的掩码元素屏蔽的结果数据元素包括一个被屏蔽的值。 公开了其它方法，装置，系统和指令。
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2.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING AN ABSOLUTE DIFFERENCE CALCULATION BETWEEN CORRESPONDING PACKED DATA ELEMENTS OF TWO VECTOR REGISTERS 审中-公开用于执行两个矢量寄存器的包装数据元素之间的绝对差分计算的系统，设备和方法
公开(公告)号：WO2013095597A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067067
申请日：2011-12-22
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , HAGOG, Mostafa , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev
Inventor： OULD-AHMED-VALL, Elmoustapha , HAGOG, Mostafa , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev
CPC classification number: G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F17/10
Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor absolute difference calculation in response to a single vector packed absolute difference instruction that includes a first and second source vector register operand, a destination vector register operand, and an opcode are described.
Abstract translation: 描述了响应于包括第一和第二源向量寄存器操作数，目的向量寄存器操作数和操作码的单向量压缩绝对差指令在计算机处理器中执行绝对差计算的系统，装置和方法的实施例。
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公开(公告)号：WO2013095463A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066628
申请日：2011-12-21
Applicant: INTEL CORPORATION , PINEIRO, Jose-Alejandro , RUBANOVICH, Simon , EITAN, Benny , GRADSTEIN, Amit , FLETCHER, Thomas D.
Inventor： PINEIRO, Jose-Alejandro , RUBANOVICH, Simon , EITAN, Benny , GRADSTEIN, Amit , FLETCHER, Thomas D.
CPC classification number: G06F7/57 , G06F1/02 , G06F1/03 , G06F1/0356 , G06F7/544 , G06F7/552 , G06F9/30014 , G06F9/3832 , G06F2101/08 , G06F2101/10 , G06F2101/12 , G06F2207/5521
Abstract: A math circuit for computing an estimate of a transcendental function is described. A lookup table storage circuit has stored therein several groups of binary values, where each group of values represents a respective coefficient of a first polynomial that estimates the function to a high precision. A first computing circuit uses a binary value from each group of values, to evaluate the first polynomial. A second computing circuit uses a portion of a binary value, that is also taken from one of the groups of values, to evaluate a second polynomial that estimates the function to a low precision. Other embodiments are also described and claimed.
Abstract translation: 描述了一种用于计算超验函数估计的数学电路。 查找表存储电路中存储有几组二进制值，其中每组值表示将功能估计为高精度的第一多项式的相应系数。 第一计算电路使用来自每组值的二进制值来评估第一多项式。 第二计算电路使用二进制值的一部分，其也取自值组中的一组，以评估将功能估计为低精度的第二多项式。 还描述和要求保护其他实施例。
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4.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A HORIZONTAL ADD OR SUBTRACT IN RESPONSE TO A SINGLE INSTRUCTION 审中-公开用于对单一指令执行水平添加或分类的系统，设备和方法
公开(公告)号：WO2013095658A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067246
申请日：2011-12-23
Applicant: INTEL CORPORATION , HAGOG, Mostafa , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev
Inventor： HAGOG, Mostafa , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev
CPC classification number: G06F9/30036 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30167 , G06F9/30185 , G06F15/8053 , G06F2207/5442
Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, and an opcode are describes.
Abstract translation: 用于在计算机处理器中执行的系统，装置和方法的实施例，其响应于包括目的地向量寄存器操作数，源向量寄存器操作数，单向量压缩水平加法或减法指令，对打包数据元素进行水平加减， 并且描述操作码。
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公开(公告)号：WO2013095620A9
公开(公告)日：2013-06-27
申请号：PCT/US2011/067097
申请日：2011-12-23
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret, L. , CHARNEY, Mark, J. , SPERBER, Zeev , GRADSTEIN, Amit
Inventor： OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret, L. , CHARNEY, Mark, J. , SPERBER, Zeev , GRADSTEIN, Amit
Abstract: An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.
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Patent Agency Ranking6.发明申请PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO GENERATE SEQUENCES OF INTEGERS IN NUMERICAL ORDER THAT DIFFER BY A CONSTANT STRIDE 审中-公开处理器，方法，系统和指令，用于生成恒定序列的数字序列中的整数序列
公开(公告)号：WO2013095564A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067014
申请日：2011-12-22
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , ABRAHAM, Seth , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
Inventor： OULD-AHMED-VALL, Elmoustapha , ABRAHAM, Seth , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
CPC classification number: G06F9/30181 , G06F9/30018 , G06F9/30032 , G06F9/30036
Abstract: A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four non-negative integers in numerical order with all integers in consecutive positions differing by a constant stride of at least two. In an aspect, storing the result including the sequence of the at least four integers is performed without calculating the at least four integers using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
Abstract translation: 一方面的方法包括接收指示目的地存储位置的指令。 结果存储在目的地存储位置以响应该指令。 结果包括以数字顺序的至少四个非负整数的序列，其中连续位置中的所有整数与至少两个的恒定步幅相差。 在一方面，使用前一条指令的结果，在不计算至少四个整数的情况下执行存储包括至少四个整数的序列的结果。 公开了其它方法，装置，系统和指令。
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7.发明申请PACKED DATA REARRANGEMENT CONTROL INDEXES PRECURSORS GENERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开包装数据重新布置控制指标前提条件生成处理器，方法，系统和说明
公开(公告)号：WO2013095563A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067013
申请日：2011-12-22
Applicant: INTEL CORPORATION , ABRAHAM, Seth , VALENTINE, Robert , OULD-AHMED-VALL, Elmoustapha , SPERBER, Zeev , GRADSTEIN, Amit
Inventor： ABRAHAM, Seth , VALENTINE, Robert , OULD-AHMED-VALL, Elmoustapha , SPERBER, Zeev , GRADSTEIN, Amit
CPC classification number: G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30036
Abstract: A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
Abstract translation: 一方面的方法包括接收指示目的地存储位置的指令。 结果存储在目的地存储位置以响应该指令。 结果包括结果，包括至少四个非负整数的序列。 在一个方面，使用前一条指令的结果不计算至少四个非负整数的值。 公开了其它方法，装置，系统和指令。
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公开(公告)号：WO2013095535A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066955
申请日：2011-12-22
Applicant: INTEL CORPORATION , SAN ADRIAN, Jesus Corbal , ANDERSON, Cristina S. , VALENTINE, Robert , TOLL, Bret L. , GRADSTEIN, Amit , RUBANOVICH, Simon , EITAN, Benny
Inventor： SAN ADRIAN, Jesus Corbal , ANDERSON, Cristina S. , VALENTINE, Robert , TOLL, Bret L. , GRADSTEIN, Amit , RUBANOVICH, Simon , EITAN, Benny
CPC classification number: G06F9/3001 , G06F9/30014 , G06F9/30036
Abstract: A method of an aspect includes receiving a floating point rounding instruction. The floating point rounding instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point that each of the one or more floating point data elements are to be rounded to, and indicates a destination storage location. A result is stored in the destination storage location in response to the floating point rounding instruction. The result includes one or more rounded result floating point data elements. Each of the one or more rounded result floating point data elements includes one of the floating point data elements of the source, in a corresponding position, which has been rounded to the indicated number of fraction bits. Other methods, apparatus, systems, and instructions are disclosed.
Abstract translation: 一方面的方法包括接收浮点舍入指令。 浮点舍入指令指示一个或多个浮点数据元素的源，指示在一个或多个浮点数据元素中的每一个要四舍五入的基数点之后的分数比特的数量，并且指示目的地存储位置 。 响应于浮点舍入指令，结果存储在目的地存储位置。 结果包括一个或多个舍入结果浮点数据元素。 一个或多个圆化结果浮点数据元素中的每一个包括源的浮点数据元素中的一个，在对应位置中，其被舍入到所指示的小数位数。 公开了其它方法，装置，系统和指令。
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公开(公告)号：WO2013095637A9
公开(公告)日：2013-06-27
申请号：PCT/US2011/067210
申请日：2011-12-23
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , SPERBER, Zeev , GRADSTEIN, Amit
Inventor： OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , CORBAL, Jesus , TOLL, Bret L. , CHARNEY, Mark J. , SPERBER, Zeev , GRADSTEIN, Amit
Abstract: An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
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10.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A BUTTERFLY HORIZONTAL AND CROSS ADD OR SUBSTRACT IN RESPONSE TO A SINGLE INSTRUCTION 审中-公开系统，设备和方法，用于执行水平和横向添加或影响单一指令
公开(公告)号：WO2013095631A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067183
申请日：2011-12-23
Applicant: INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , HAGOG, Mostafa , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev
Inventor： OULD-AHMED-VALL, Elmoustapha , HAGOG, Mostafa , VALENTINE, Robert , GRADSTEIN, Amit , RUBANOVICH, Simon , SPERBER, Zeev
CPC classification number: G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F17/142
Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed butterfly horizontal cross add or subtract of packed data elements in response to a single vector packed butterfly horizontal cross add or subtract instruction that includes a destination vector register operand, a source vector register operand, an immediate, and an opcode are described.
Abstract translation: 用于在计算机处理器中执行向量包装蝶形水平交叉加法或减法的系统，装置和方法响应于包括目的地向量寄存器操作数的单向量包装蝶式水平交叉加减法指令，源 描述向量寄存器操作数，立即数和操作码。
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