公开(公告)号：WO2008103885A3

公开(公告)日：2008-10-16

申请号：PCT/US2008054685

申请日：2008-02-22

Applicant: TEXAS INSTRUMENTS INC ,  WON NARA ,  HUNG CHING-YU

Inventor： WON NARA ,  HUNG CHING-YU

IPC: G06F9/26 ,  G06F9/34 ,  G06F12/00

CPC classification number: G06F17/18 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30098

Abstract: An extension to current multiple memory bank (309) video processing architecture is presented. A more powerful memory controller (310, 311) is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths (316) making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.

Abstract translation: 介绍了当前多存储体（309）视频处理体系结构的扩展。 结合更强大的存储器控​​制器（310,311），允许在输入和输出数据路径（316）处计算多个存储器地址，使得可能在输入和输出端口处进行读取和写入的新组合。 用于图像和视频处理的算法所需的矩阵转置计算在MAC模块和存储体中实现。 这里描述的技术可以应用于其他并行处理器，包括未来的VLIW DSP处理器。

公开(公告)号：WO2008103885A2

公开(公告)日：2008-08-28

申请号：PCT/US2008/054685

申请日：2008-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  WON, Nara ,  HUNG, Ching-Yu

Inventor： WON, Nara ,  HUNG, Ching-Yu

IPC: G06F17/14

CPC classification number: G06F17/18 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30098

Abstract: An extension to current multiple memory bank (309) video processing architecture is presented. A more powerful memory controller (310, 311) is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths (316) making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.

Abstract translation: 介绍了当前多存储器（309）视频处理架构的扩展。 结合了更强大的存储器控​​制器（310,311），允许在输入和输出数据路径（316）处计算多个存储器地址，使得在输入和输出端口处的读取和写入成为新的组合。 在图像和视频处理中使用的算法所需的矩阵转置计算在MAC模块和存储器中实现。 这里描述的技术可以应用于其他并行处理器，包括将来的VLIW DSP处理器。