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    AN INTEGRATED MEMORY CORE AND MEMORY INTERFACE CIRCUIT
    1.
    发明申请
    AN INTEGRATED MEMORY CORE AND MEMORY INTERFACE CIRCUIT 审中-公开
    集成存储器核心和存储器接口电路

    公开(公告)号：WO2007002324A2

    公开(公告)日：2007-01-04

    申请号：PCT/US2006024360

    申请日：2006-06-23

    Applicant: METARAM INC ,  RAJAN SURESH N

    Inventor： RAJAN SURESH N

    IPC: G11C29/00

    CPC classification number: G11C29/50 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50012 ,  G11C2207/2254

    Abstract: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.

    Abstract translation: 存储器件包括第一和第二集成电路管芯。 第一集成电路管芯包括存储器芯以及第一接口电路。 第一接口电路允许完全访问存储器单元（例如，对存储器单元的读取，写入，激活，预充电和刷新操作）。 第二集成电路管芯包括第二接口，其经由第一接口电路将存储器核与外部总线（例如到外部总线的同步接口）接口。 一种技术将存储器核心集成电路管芯与接口集成电路管芯组合，以配置存储器件。 对存储器芯集成电路管芯进行速度测试，并且基于存储器芯集成电路管芯的速度将接口集成电路管芯电耦合到存储器芯集成电路管芯。

    METHODS AND APPARATUS OF STACKING DRAMS
    3.
    发明申请
    METHODS AND APPARATUS OF STACKING DRAMS 审中-公开
    堆叠工艺的方法与装置

    公开(公告)号：WO2007028109A3

    公开(公告)日：2008-01-10

    申请号：PCT/US2006034390

    申请日：2006-09-01

    Applicant: METARAM INC ,  RAJAN SURESH ,  SMITH MICHAEL ,  WANG DAVID

    Inventor： RAJAN SURESH ,  SMITH MICHAEL ,  WANG DAVID

    IPC: G11C8/00

    CPC classification number: G11C7/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4093 ,  G11C29/812

    Abstract: Large capacity memory systems (FB-DIMMs) are constructed using stacked memory integrated circuits (220) or chips (310). The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

    Abstract translation: 使用堆叠存储器集成电路（220）或芯片（310）构建大容量存储器系统（FB-DIMM）。 堆叠的存储器芯片被构造成在满足当前和将来的存储器标准的同时消除诸如信号完整性的问题。

    AN INTEGRATED MEMORY CORE AND MEMORY INTERFACE CIRCUIT
    6.
    发明申请
    AN INTEGRATED MEMORY CORE AND MEMORY INTERFACE CIRCUIT 审中-公开

    公开(公告)号：WO2007002324A3

    公开(公告)日：2007-01-04

    申请号：PCT/US2006/024360

    申请日：2006-06-23

    Applicant: METARAM, INC. ,  RAJAN, Suresh, N.

    Inventor： RAJAN, Suresh, N.

    IPC: G11C5/06 ,  G06F13/00

    Abstract: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells ( e.g. , reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.

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