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    A METHOD FOR CALIBRATING THE READ LATENCY OF A DDR DRAM MODULE
    1.
    发明申请
    A METHOD FOR CALIBRATING THE READ LATENCY OF A DDR DRAM MODULE 审中-公开
    一种用于校准DDR DRAM模块读取时间的方法

    公开(公告)号：WO2016203490A2

    公开(公告)日：2016-12-22

    申请号：PCT/IN2016/000152

    申请日：2016-06-13

    Applicant: GYAN, Prakash ,  NIDHIR, Kumar ,  CHANDRASHEKAR, Narla

    Inventor： GYAN, Prakash ,  NIDHIR, Kumar ,  CHANDRASHEKAR, Narla

    IPC: G11C11/00

    CPC classification number: G11C29/028 ,  G11C11/401 ,  G11C29/023 ,  G11C29/50012

    Abstract: A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations in the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.

    Abstract translation: 设想了一种用于自动校准存储器模块的读等待时间的方法。 读延迟最初设置为默认最大值。 默认最大值等于完成数据读取操作所需的时钟周期数。 鉴于考虑到默认最大值从存储器模块读取的数据模式。 执行存储器读取操作，并且根据默认最大值捕获第一数据模式。 将识别的数据模式与第一数据模式进行比较，并且基于其比较来迭代地校准默认最大值。 在多个存储器读取操作中重复上述步骤，并且跟踪最大默认值的变化，并且基于此计算平均最大值。 平均最大值被分配为内存模块的读取延迟。

    TIMING-DRIFT CALIBRATION
    2.
    发明申请
    TIMING-DRIFT CALIBRATION 审中-公开
    定时漂移校准

    公开(公告)号：WO2012082274A3

    公开(公告)日：2012-08-16

    申请号：PCT/US2011060213

    申请日：2011-11-10

    Applicant: RAMBUS INC ,  FRANS YOHAN U ,  ELLIS WAYNE F ,  BANSAL AKASH

    Inventor： FRANS YOHAN U ,  ELLIS WAYNE F ,  BANSAL AKASH

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C29/50012 ,  G01R23/02 ,  G01R23/15 ,  G01R35/005 ,  G06F1/08 ,  G06F1/12 ,  G06F11/1604 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03L1/02

    Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.

    Abstract translation: 所公开的实施例涉及支持定时漂移校准的存储器系统的组件。 在具体实施例中，该存储器系统包含存储器设备（或多个设备），其包括时钟分配电路和可产生频率的振荡器电路，其中频率的改变指示时钟分配电路的时序漂移。 存储器件还包括被配置为测量振荡器电路的频率的测量电路。 另外，存储器系统包含存储器控制器，该存储器控制器可以向存储器装置发送请求以触发存储器装置测量振荡器电路的频率。 存储器控制器还被配置为从存储器装置接收测量的频率并且使用测量的频率来确定存储器装置中的时序漂移。

    出力装置および試験装置
    3.
    发明申请
    出力装置および試験装置 审中-公开
    输出设备和测试设备

    公开(公告)号：WO2010095378A1

    公开(公告)日：2010-08-26

    申请号：PCT/JP2010/000637

    申请日：2010-02-03

    Applicant: 株式会社アドバンテスト ,  市川 弘毅

    Inventor： 市川　弘毅

    IPC: H03K5/12 ,  G01R31/28

    CPC classification number: H03K5/04 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56 ,  H03K19/00361

    Abstract: 　入力信号に応じた出力信号を出力する出力装置であって、それぞれが入力信号に応じた波形の中間信号を出力する複数のドライバと、複数のドライバのそれぞれから出力された中間信号を加算して、出力信号として出力する加算部と、指定されたスルーレートに応じて、複数のドライバ間における、入力信号が変化し始めてから中間信号が変化し始めるまでの遅延量の差を設定する制御部と、を備える出力装置を提供する。

    Abstract translation: 输出装置响应于输入信号输出输出信号，该输出装置设置有多个驱动器，每个驱动器输出与输入信号相对应的波形的中间信号; 添加单元，将从所述多个驱动器输出的中间信号相加，并输出所述结果作为输出信号; 以及控制单元，其响应于所指定的转换速率，将从输入信号的变化开始到中间信号的变化开始之间的多个驱动器之间的延迟量的差设定。

    MEMORY SYSTEM WITH COMMAND FILTERING
    4.
    发明申请
    MEMORY SYSTEM WITH COMMAND FILTERING 审中-公开
    带命令过滤的内存系统

    公开(公告)号：WO2010065290A2

    公开(公告)日：2010-06-10

    申请号：PCT/US2009/064813

    申请日：2009-11-17

    Applicant: RAMBUS INC. ,  WARE, Frederick, A. ,  RICHARDSON, Wayne ,  KASAMSETTY, Kishore

    Inventor： WARE, Frederick, A. ,  RICHARDSON, Wayne ,  KASAMSETTY, Kishore

    IPC: G06F13/32 ,  G06F13/24 ,  G06F11/10 ,  G06F12/00

    CPC classification number: G11C29/56 ,  G01R31/3171 ,  G11C29/028 ,  G11C29/48 ,  G11C29/50012 ,  G11C29/56012

    Abstract: A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode.

    Abstract translation: 存储器系统包括经由高速数据和请求链路耦合到至少一个存储器设备的存储器控​​制器。 定期校准链路的时间和电压裕度，以减少误码。 高速请求链接使校准复杂化，因为通过未校准的请求链接发布的命令可能被存储器设备错误地解释。 错误解释的命令会破坏校准过程（例如，写入命令可能被错误解释为断电命令）。 内存控制器使用单独的低速控制接口来解决此问题，以发出过滤器命令，指示内存设备在校准模式下拒绝潜在的破坏性请求。

    AN INTEGRATED MEMORY CORE AND MEMORY INTERFACE CIRCUIT
    6.
    发明申请
    AN INTEGRATED MEMORY CORE AND MEMORY INTERFACE CIRCUIT 审中-公开
    集成存储器核心和存储器接口电路

    公开(公告)号：WO2007002324A2

    公开(公告)日：2007-01-04

    申请号：PCT/US2006024360

    申请日：2006-06-23

    Applicant: METARAM INC ,  RAJAN SURESH N

    Inventor： RAJAN SURESH N

    IPC: G11C29/00

    CPC classification number: G11C29/50 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50012 ,  G11C2207/2254

    Abstract: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.

    Abstract translation: 存储器件包括第一和第二集成电路管芯。 第一集成电路管芯包括存储器芯以及第一接口电路。 第一接口电路允许完全访问存储器单元（例如，对存储器单元的读取，写入，激活，预充电和刷新操作）。 第二集成电路管芯包括第二接口，其经由第一接口电路将存储器核与外部总线（例如到外部总线的同步接口）接口。 一种技术将存储器核心集成电路管芯与接口集成电路管芯组合，以配置存储器件。 对存储器芯集成电路管芯进行速度测试，并且基于存储器芯集成电路管芯的速度将接口集成电路管芯电耦合到存储器芯集成电路管芯。

    SELF-ADAPTIVE PROGRAM DELAY CIRCUITRY FOR PROGRAMMABLE MEMORIES
    8.
    发明申请
    SELF-ADAPTIVE PROGRAM DELAY CIRCUITRY FOR PROGRAMMABLE MEMORIES 审中-公开
    自适应程序延迟电路可编程存储器

    公开(公告)号：WO2006023146A2

    公开(公告)日：2006-03-02

    申请号：PCT/US2005024187

    申请日：2005-07-11

    Applicant: ATMEL CORP

    Inventor： COMBE MARYLENE ,  DAGA JEAN-MICHEL

    IPC: G11C7/06 ,  G11C11/34

    CPC classification number: G11C16/10 ,  G11C16/04 ,  G11C16/3459 ,  G11C29/028 ,  G11C29/50012 ,  G11C2216/14

    Abstract: A self-adaptive programming circuit (150, 160, 173, 170, 175, 154, 103) for EEPROM (Fig. 2) is used to automatically tune an erase or write delay, providing an improved programming window. The programming circuit may also provide improvements in data retention for programmed memory cells. The invention can be applied more particularly in the field of EEPROM memories capable of page mode writing operations.

    Abstract translation: 用于EEPROM（图2）的自适应编程电路（150,160,173,170,175,154,103）用于自动调整擦除或写入延迟，从而提供改进的编程窗口。 编程电路还可以提供对编程的存储器单元的数据保留的改进。 本发明可以更具体地应用于能够进行页面模式写入操作的EEPROM存储器领域。

    DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS
    9.
    发明申请
    DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS 审中-公开
    用于通信信道的移动跟踪反馈

    公开(公告)号：WO2005089407A3

    公开(公告)日：2005-12-22

    申请号：PCT/US2005008830

    申请日：2005-03-16

    Applicant: RAMBUS INC ,  BEST SCOTT C ,  ABHYANKAR ABHIJIT M ,  CHANG KUN-YUNG ,  LAMBRECHT FRANK

    Inventor： BEST SCOTT C ,  ABHYANKAR ABHIJIT M ,  CHANG KUN-YUNG ,  LAMBRECHT FRANK

    IPC: G06F1/04 ,  H04L7/00 ,  H04L7/10 ,  H04L25/14

    CPC classification number: G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

    Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

    Abstract translation: 通信信道包括具有耦合到正常信号源的发射器​​的第一组件和具有耦合到正常信号目的地的接收器的第二组件。 通信链路耦合第一和第二组件。 校准逻辑规定为通信信道的参数设置操作值，例如通过在链路初始化时执行穷举校准序列。 包括监测功能的跟踪电路通过监测具有与通信信道中的漂移相关的特性的反馈信号来跟踪参数中的漂移，并且更新或指示需要更新参数的操作值 响应监测功能。

    CONFIGURABLE WIDTH BUFFERED MODULE HAVING A BYPASS CIRCUIT
    10.
    发明申请
    CONFIGURABLE WIDTH BUFFERED MODULE HAVING A BYPASS CIRCUIT 审中-公开
    具有旁路电路的可配置宽度缓冲模块

    公开(公告)号：WO2005116838A1

    公开(公告)日：2005-12-08

    申请号：PCT/US2005/017066

    申请日：2005-05-16

    Applicant: RAMBUS INCORPORATED ,  PEREGO, Richard ,  WARE, Fred ,  TSERN, Ely ,  HAMPEL, Craig

    Inventor： PEREGO, Richard ,  WARE, Fred ,  TSERN, Ely ,  HAMPEL, Craig

    IPC: G06F12/00

    CPC classification number: G11C5/04 ,  G06F13/1684 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1806 ,  H05K1/181

    Abstract: A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one bypass circuit. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. The configurable width buffer device is coupled to at least one memory device (by way of an internal channel), entry pin and exit pin on the memory module. The configurable width buffer device includes a multiplexer/demultiplexer circuit coupled to the entry pin and the internal channel for accessing the memory device. A bypass circuit is coupled to the entry pin and the exit pin in order to allow information to be transferred through the memory module to another coupled memory module in the memory system by way of an external channel. In an alternate embodiment of the present invention, two bypass circuits are coupled to a pair of entry and exit pins. In an embodiment of the present invention, a memory system may include at least four interfaces, or sockets, for respective memory modules having configurable width buffer devices with bypass circuits that enable additional upgrade options while reducing memory system access delays.

    Abstract translation: 存储器系统架构/互连拓扑包括具有可配置宽度缓冲器件的可配置宽度缓冲存储器模块，其具有至少一个旁路电路。 诸如可配置的宽度缓冲器装置之类的缓冲装置被定位在位于诸如DIMM之类的存储器模块的衬底表面上的至少一个集成电路存储器件之间或之间。 可配置宽度缓冲器件耦合到存储器模块上的至少一个存储器件（通过内部通道），入口引脚和引脚。 可配置宽度缓冲器件包括耦合到入口引脚和用于访问存储器件的内部通道的多路复用器/解复用器电路。 旁路电路耦合到入口引脚和出口引脚，以便允许信息通过存储器模块通过外部通道传送到存储器系统中的另一个耦合的存储器模块。 在本发明的替代实施例中，两个旁路电路耦合到一对入口和出口销。 在本发明的一个实施例中，存储器系统可以包括至少四个接口或插座，用于具有可配置的宽度缓冲器设备的相应存储器模块，该旁路电路能够实现额外的升级选项，同时减少存储器系统访问延迟。

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