公开(公告)号：WO2007061703A3

公开(公告)日：2007-05-31

申请号：PCT/US2006/044252

申请日：2006-11-13

Applicant: INTEL CORPORATION ,  GALBI, Duane, E. ,  LOBOPRABHU, Ranjit ,  NIELL, Jose

Inventor： GALBI, Duane, E. ,  LOBOPRABHU, Ranjit ,  NIELL, Jose

IPC: G06F11/10

Abstract: Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.

公开(公告)号：WO2006039183A3

公开(公告)日：2006-04-13

申请号：PCT/US2005/034010

申请日：2005-09-21

Applicant: INTEL CORPORATION ,  WOLRICH, Gilbert ,  ROSENBLUTH, Mark ,  ADILETTA, Matthew ,  WILKINSON, Hugh ,  NIELL, Jose ,  NARAYANAN, Rajagopal ,  JAIN, Sanjeev

Inventor： WOLRICH, Gilbert ,  ROSENBLUTH, Mark ,  ADILETTA, Matthew ,  WILKINSON, Hugh ,  NIELL, Jose ,  NARAYANAN, Rajagopal ,  JAIN, Sanjeev

IPC: G06F9/32

Abstract: Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.

公开(公告)号：WO2007061703A2

公开(公告)日：2007-05-31

申请号：PCT/US2006044252

申请日：2006-11-13

Applicant: INTEL CORP ,  GALBI DUANE E ,  LOBOPRABHU RANJIT ,  NIELL JOSE

Inventor： GALBI DUANE E ,  LOBOPRABHU RANJIT ,  NIELL JOSE

CPC classification number: G06F11/1032

Abstract: Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.

Abstract translation: 用于执行用于高速实现的纠错码（ECC）编码技术的方法和装置。 ECC代码字被构造为促进非常快速的单错误检测（SED），其允许在检测到错误时在一个周期内停止状态机，并使相应的单错误校正（SEC）操作成为 在状态机处于暂停模式时，执行多个周期。

公开(公告)号：WO2006039183A2

公开(公告)日：2006-04-13

申请号：PCT/US2005034010

申请日：2005-09-21

Applicant: INTEL CORP ,  WOLRICH GILBERT ,  ROSENBLUTH MARK ,  ADILETTA MATTHEW ,  WILKINSON HUGH ,  NIELL JOSE ,  NARAYANAN RAJAGOPAL ,  JAIN SANJEEV

Inventor： WOLRICH GILBERT ,  ROSENBLUTH MARK ,  ADILETTA MATTHEW ,  WILKINSON HUGH ,  NIELL JOSE ,  NARAYANAN RAJAGOPAL ,  JAIN SANJEEV

IPC: G06F9/32

CPC classification number: G06F12/0607 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3851

Abstract: Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.

Abstract translation: 通过使用交错寻址方案共享相邻控制存储器来支持计算引擎代码空间的扩展的方法和装置。 与原始指令线程相对应的指令被划分为存储在相应控制存储器中的多个交错序列。 在线程执行期间，基于交织方案以重复的顺序从控制存储器检索指令。 例如，在一个实施例中，两个计算引擎共享两个控制存储。 因此，给定线程的指令以交替方式从控制存储器顺序加载。 在另一个实施例中，四个控制存储由四个计算引擎共享。 在这种情况下，线程中的指令使用四个存储进行交织，并且每个存储在代码序列中每第四个指令被访问。 还提供了处理分支操作以维持对控制存储的同步访问的方案。