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    METHOD AND APPARATUS TO SUPPORT MULTIPLE MEMORY BANKS WITH A MEMORY BLOCK
    1.
    发明申请
    METHOD AND APPARATUS TO SUPPORT MULTIPLE MEMORY BANKS WITH A MEMORY BLOCK 审中-公开
    用存储块支持多个存储器的方法和装置

    公开(公告)号：WO2006069126A3

    公开(公告)日：2006-11-23

    申请号：PCT/US2005046297

    申请日：2005-12-20

    Applicant: INTEL CORP ,  JAIN SANJEEV ,  WOLRICH GILBERT ,  ROSENBLUTH MARK ,  BERNSTEIN DEBRA

    Inventor： JAIN SANJEEV ,  WOLRICH GILBERT ,  ROSENBLUTH MARK ,  BERNSTEIN DEBRA

    IPC: G06F13/16

    CPC classification number: G06F13/1673

    Abstract: A memory controller system includes a memory command storage module to store commands for a plurality of memory banks. The system includes a plurality of control mechanisms, each of which includes first and second pointers, to provide, in combination with a next field in each module location, a link list of commands for a given one of the plurality of memory banks.

    Abstract translation: 存储器控制器系统包括用于存储多个存储器组的命令的存储器命令存储模块。 该系统包括多个控制机制，每个控制机制包括第一和第二指针，以便与每个模块位置中的下一个区域组合提供多个存储体中给定的一个存储体的命令的链接列表。

    METHOD AND APPARATUS TO SUPPORT MULTIPLE MEMORY BANKS WITH A MEMORY BLOCK
    3.
    发明申请
    METHOD AND APPARATUS TO SUPPORT MULTIPLE MEMORY BANKS WITH A MEMORY BLOCK 审中-公开
    用存储器块支持多个存储器银行的方法和设备

    公开(公告)号：WO2006069126A2

    公开(公告)日：2006-06-29

    申请号：PCT/US2005/046297

    申请日：2005-12-20

    Applicant: INTEL CORPORATION ,  JAIN, Sanjeev ,  WOLRICH, Gilbert ,  ROSENBLUTH, Mark ,  BERNSTEIN, Debra

    Inventor： JAIN, Sanjeev ,  WOLRICH, Gilbert ,  ROSENBLUTH, Mark ,  BERNSTEIN, Debra

    IPC: G06F13/16

    CPC classification number: G06F13/1673

    Abstract: A memory controller system includes a memory command storage module to store commands for a plurality of memory banks. The system includes a plurality of control mechanisms, each of which includes first and second pointers, to provide, in combination with a next field in each module location, a link list of commands for a given one of the plurality of memory banks.

    Abstract translation: 存储器控制器系统包括用于存储用于多个存储体的命令的存储器命令存储模块。 该系统包括多个控制机构，每个控制机构包括第一和第二指针，以与每个模块位置中的下一个字段结合提供用于多个存储体中给定的一个存储体的命令的链接列表。 p>

    IN-LINE WAFER THICKNESS SENSING
    5.
    发明申请
    IN-LINE WAFER THICKNESS SENSING 审中-公开
    在线晶圆厚度感应

    公开(公告)号：WO2010053924A3

    公开(公告)日：2010-08-12

    申请号：PCT/US2009063161

    申请日：2009-11-03

    Applicant: APPLIED MATERIALS INC ,  SIN GARRETT H ,  JAIN SANJEEV ,  SWEDEK BOGUSLAW A ,  KARUPPIAH LAKSHMANAN

    Inventor： SIN GARRETT H ,  JAIN SANJEEV ,  SWEDEK BOGUSLAW A ,  KARUPPIAH LAKSHMANAN

    IPC: H01L21/66 ,  H01L21/304

    CPC classification number: B24B37/013 ,  B24B49/02 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming bare silicon substrates is described. A bare silicon substrate is measured, wherein measuring is performed by a non-contact capacitance measurement device to obtain a signal at a point on the substrate. The signal or a thickness indicated by the signal is communicated to a controller. An adjusted polishing parameter according to the signal or thickness indicated by the signal is determined. After determining an adjusted polishing parameter, the bare silicon substrate is polished on a polisher using the adjusted polishing parameter.

    Abstract translation: 描述了形成裸硅衬底的方法。 测量裸露的硅衬底，其中通过非接触电容测量装置进行测量以在衬底上的某点处获得信号。 信号指示的信号或厚度被传送到控制器。 根据由信号指示的信号或厚度来确定调整后的抛光参数。 在确定调整的抛光参数之后，使用调整后的抛光参数在抛光机上抛光裸硅衬底。

    EXPANSION OF COMPUTE ENGINE CODE SPACE BY SHARING ADJACENT CONTROL STORES USING INTERLEAVED PROGRAM ADDRESSES
    8.
    发明申请
    EXPANSION OF COMPUTE ENGINE CODE SPACE BY SHARING ADJACENT CONTROL STORES USING INTERLEAVED PROGRAM ADDRESSES 审中-公开
    通过使用独立程序地址共享相似控制存储来扩展计算机引擎代码空间

    公开(公告)号：WO2006039183A2

    公开(公告)日：2006-04-13

    申请号：PCT/US2005034010

    申请日：2005-09-21

    Applicant: INTEL CORP ,  WOLRICH GILBERT ,  ROSENBLUTH MARK ,  ADILETTA MATTHEW ,  WILKINSON HUGH ,  NIELL JOSE ,  NARAYANAN RAJAGOPAL ,  JAIN SANJEEV

    Inventor： WOLRICH GILBERT ,  ROSENBLUTH MARK ,  ADILETTA MATTHEW ,  WILKINSON HUGH ,  NIELL JOSE ,  NARAYANAN RAJAGOPAL ,  JAIN SANJEEV

    IPC: G06F9/32

    CPC classification number: G06F12/0607 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3851

    Abstract: Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.

    Abstract translation: 通过使用交错寻址方案共享相邻控制存储器来支持计算引擎代码空间的扩展的方法和装置。 与原始指令线程相对应的指令被划分为存储在相应控制存储器中的多个交错序列。 在线程执行期间，基于交织方案以重复的顺序从控制存储器检索指令。 例如，在一个实施例中，两个计算引擎共享两个控制存储。 因此，给定线程的指令以交替方式从控制存储器顺序加载。 在另一个实施例中，四个控制存储由四个计算引擎共享。 在这种情况下，线程中的指令使用四个存储进行交织，并且每个存储在代码序列中每第四个指令被访问。 还提供了处理分支操作以维持对控制存储的同步访问的方案。

    BUFFER CIRCUIT
    9.
    发明申请
    BUFFER CIRCUIT 审中-公开
    缓冲电路

    公开(公告)号：WO2004100376A9

    公开(公告)日：2005-11-17

    申请号：PCT/IB2004050613

    申请日：2004-05-07

    Applicant: KONINKL PHILIPS ELECTRONICS NV ,  KATOCH ATUL ,  JAIN SANJEEV K ,  MEIJER RINZE I M P

    Inventor： KATOCH ATUL ,  JAIN SANJEEV K ,  MEIJER RINZE I M P

    IPC: H03K19/00 ,  H03K19/003

    CPC classification number: H03K19/00361 ,  H03K19/0027

    Abstract: A buffer circuit (31), for example a repeater or receiver circuit for a signal wire of an on-chip bus, receives an input signal, and produces an output signal. The buffer circuit (31) comprises a first inverting stage (7) and a second inverter stage (9). The second inverting stage (9) provides the drive for the output (5). The first inverting stage (7) has additional circuitry (15, 17, 19, 21, 23, 25, 27, 29) for controlling the strengths of the pull up path and the pull down path. The pull up/down paths are dynamically controlled according to the status of one or more aggressor signals. In one embodiment the switching threshold is lowered only in the worst case delay scenario, i.e. when the signal wire (3) is at a different logic level to the aggressor signals. In another embodiment, the switching threshold is raised when the signal wire and aggressor signals are all at the same logic level, thereby reducing crosstalk.

    Abstract translation: 缓冲电路（31）例如用于片上总线的信号线的中继器或接收器电路接收输入信号，并产生输出信号。 缓冲电路（31）包括第一反相级（7）和第二反相器级（9）。 第二反相级（9）为输出（5）提供驱动。 第一反相级（7）具有用于控制上拉路径和下拉路径的强度的附加电路（15,17,19,21,23,25,27,29）。 根据一个或多个攻击者信号的状态来动态地控制上拉/下拉路径。 在一个实施例中，切换阈值仅在最差情况下延迟情况下降低，即当信号线（3）与侵略者信号处于不同的逻辑电平时。 在另一个实施例中，当信号线和侵扰器信号都处于相同的逻辑电平时，开关阈值升高，从而减少串扰。

    BUFFER CIRCUIT
    10.
    发明申请
    BUFFER CIRCUIT 审中-公开
    缓冲电路

    公开(公告)号：WO2004100376A1

    公开(公告)日：2004-11-18

    申请号：PCT/IB2004/050613

    申请日：2004-05-07

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  KATOCH, Atul ,  JAIN, Sanjeev, K. ,  MEIJER, Rinze, I., M., P.

    Inventor： KATOCH, Atul ,  JAIN, Sanjeev, K. ,  MEIJER, Rinze, I., M., P.

    IPC: H03K19/003

    CPC classification number: H03K19/00361 ,  H03K19/0027

    Abstract: A buffer circuit (31), for example a repeater or receiver circuit for a signal wire of an on-chip bus, receives an input signal, and produces an output signal. The buffer circuit (31) comprises a first inverting stage (7) and a second inverter stage (9). The second inverting stage (9) provides the drive for the output (5). The first inverting stage (7) has additional circuitry (15, 17, 19, 21, 23, 25, 27, 29) for controlling the strengths of the pull up path and the pull down path. The pull up/down paths are dynamically controlled according to the status of one or more aggressor signals. In one embodiment the switching threshold is lowered only in the worst case delay scenario, i.e. when the signal wire (3) is at a different logic level to the aggressor signals. In another embodiment, the switching threshold is raised when the signal wire and aggressor signals are all at the same logic level, thereby reducing crosstalk.

    Abstract translation: 缓冲电路（31）例如用于片上总线的信号线的中继器或接收器电路接收输入信号并产生输出信号。 缓冲电路（31）包括第一反相级（7）和第二反相器级（9）。 第二反相级（9）为输出（5）提供驱动。 第一反相级（7）具有用于控制上拉路径和下拉路径的强度的附加电路（15,17,19,21,23,25,27,29）。 根据一个或多个攻击者信号的状态来动态地控制上拉/下拉路径。 在一个实施例中，切换阈值仅在最坏情况下延迟情况下降低，即当信号线（3）与侵略者信号处于不同的逻辑电平时。 在另一个实施例中，当信号线和侵扰器信号都处于相同的逻辑电平时，切换阈值升高，从而减少串扰。

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