公开(公告)号：WO2011073902A1

公开(公告)日：2011-06-23

申请号：PCT/IB2010/055802

申请日：2010-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ELEFTHERIOU, Evangelos S. ,  HAAS, Robert ,  MUELLER, Peter ,  PLETKA, Roman A.

Inventor： ELEFTHERIOU, Evangelos S. ,  HAAS, Robert ,  MUELLER, Peter ,  PLETKA, Roman A.

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7208

Abstract: Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.

Abstract translation: 示例性实施例包括一种用于减少基于闪存的存储器系统中的访问争用的方法，该方法包括从具有多个信道的存储器件和多个存储器块中选择具有空闲状态的芯片条带，其中芯片条带包括 多个页面，将所述条纹设置为写入状态，在所述闪存条带中的所述多个通道中的每一个上设置所述多个通道中的每一个中的写入队列头部，将写入队列头部设置到第一自由页面中 属于来自芯片条带的信道的芯片，根据写入分配调度器在信道之间分配写请求，生成页写入，并响应于页写，增加写队列头，并将芯片条设置为on 线状态当它满了。

公开(公告)号：WO2004057807A1

公开(公告)日：2004-07-08

申请号：PCT/IB2003/004837

申请日：2003-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BOWEN, Ed ,  DROZ, Patrick ,  JEFFRIES, Clark, D. ,  KENCL, Lukas ,  KIND, Andreas ,  PLETKA, Roman, A. ,  MANNAL, Soenke

Inventor： BOWEN, Ed ,  DROZ, Patrick ,  JEFFRIES, Clark, D. ,  KENCL, Lukas ,  KIND, Andreas ,  PLETKA, Roman, A. ,  MANNAL, Soenke

IPC: H04L12/56

CPC classification number: H04L47/2416 ,  H04L47/10 ,  H04L47/193 ,  H04L47/263 ,  H04L47/29 ,  H04L47/30 ,  Y02D50/10

Abstract: Methods and apparatus are provided for controlling flow rates of a plurality of data packet flows into a queue 4 corresponding to a resource 3 of a network device 1. The flows comprise a set 7 of non-responsive flows, and a set 8 of other flows which may comprise responsive flows and/or flows whose responsiveness is unknown. The flow rates are managed in accordance with a queue management scheme such that adjustments are made to each flow rate in dependence on excess bandwidth in the resource, the amounts of the adjustments being dependent on one or more adjustment parameters for each flow. An error signal is generated based on the deviation from a desired allocation ratio of the ratio of the total flow rates into the queue 4 for the sets of flows 7, 8. At least one adjustment parameter for at least one flow is then varied in dependence on the error signal in such a manner as to reduce the aforementioned deviation. A closed-loop control scheme thus operates in conjunction with the underlying queue management scheme to promote fair bandwidth allocation even in the presence of a mix of responsive and non-responsive flows.

Abstract translation: 提供了用于控制多个数据分组流到与网络设备1的资源3相对应的队列4中的流速的方法和装置。所述流包括非响应流的集合7，以及其他流的集合8 其可以包括其响应性未知的响应流和/或流。 根据队列管理方案来管理流量，使得根据资源中的过度带宽对每个流量进行调整，调整量取决于每个流的一个或多个调整参数。 基于与针对流7,8的总流量与队列4的总流量的比率的期望分配比率的偏差来生成误差信号。然后，至少一个流程的至少一个调整参数随之变化 对误差信号进行减小上述偏差的方式。 因此，闭环控制方案与底层队列管理方案一起运行，以便即使存在响应和非响应流的混合来促进公平的带宽分配。

公开(公告)号：WO2012014140A3

公开(公告)日：2012-03-22

申请号：PCT/IB2011053299

申请日：2011-07-25

Applicant: IBM ,  BUX WERNER ,  HAAS ROBERT ,  HU XIAOYU ,  PLETKA ROMAN A

Inventor： BUX WERNER ,  HAAS ROBERT ,  HU XIAOYU ,  PLETKA ROMAN A

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0246 ,  G06F12/0848 ,  G06F12/0866 ,  G06F2212/214 ,  G06F2212/221 ,  G06F2212/222 ,  G06F2212/466 ,  G06F2212/7201

Abstract: The present idea provides a high read and write performance from/to a solid state memory device. The main memory (31) of the controller (1) is not blocked by a complete address mapping table covering the entire memory device (2). Instead such table is stored in the memory device (2) itself, and only selected portions of address mapping information are buffered in the main memory (31) in a read cache (311) and a write cache (312). A separation of the read cache (311) from the write cache (312) enables an address mapping entry being evictable from the read cache (311) without the need to update the related flash memory page storing such entry in the flash memory device (2). By this design, the read cache (311) may advantageously be stored on a DRAM even without power down protection, while the write cache (312) may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.

Abstract translation: 目前的想法提供了对固态存储器设备的高读写性能。 控制器（1）的主存储器（31）不被覆盖整个存储器设备（2）的完整地址映射表阻塞。 相反，这样的表被存储在存储器设备（2）本身中，并且只有地址映射信息的所选部分被缓存在读取高速缓存（311）和写入高速缓存（312）中的主存储器（31）中。 读取高速缓存（311）与写入高速缓存（312）的分离使得地址映射条目能够从读取高速缓存（311）中逐出，而不需要更新在闪存器件（2）中存储这样的条目的相关的闪存页面 ）。 通过这种设计，即使没有断电保护，读取高速缓存（311）也可以有利地存储在DRAM上，而写入高速缓存（312）可以优选地在非易失性或其他故障安全存储器中实现。 这导致非易失性存储器或故障安全存储器的整体配置减少并且可扩展性和性能得到改善。

公开(公告)号：WO2011092641A1

公开(公告)日：2011-08-04

申请号：PCT/IB2011/050355

申请日：2011-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CIDECIYAN, Roy D. ,  ILIADIS, Ilias ,  PLETKA, Roman A.

Inventor： CIDECIYAN, Roy D. ,  ILIADIS, Ilias ,  PLETKA, Roman A.

IPC: G06F11/10

CPC classification number: G06F11/1072

Abstract: A method for decoding a codeword received from a flash memory is proposed. The flash memory comprises several multi-level flash memory cells, wherein each such multi-level flash memory cell stores one symbol of the codeword. An ECC decoder is arranged for decoding the codeword into a decoded codeword and is designed to correct a maximum number of errors. The method comprises an error check step for determining the number of errors in the codeword. If the number of errors is more than the maximum number of errors the ECC decoder can correct then at least one of a first symbol modification step and a second symbol modification step is performed. In the first symbol modification step a first modified codeword is generated by increasing the value of the symbol to the next higher value level and in the second symbol modification step a second modified codeword is generated by decreasing the value of the symbol (Si) to the next lower value level. In an analysis step the corrective effect of the symbol modification steps is calculated and in a return step the decoded codeword is determined based on the corrective effect, or an erasure of the codeword.

Abstract translation: 提出了一种用于对从闪速存储器接收的码字进行解码的方法。 闪存包括多个多级闪存单元，其中每个这样的多级闪存单元存储码字的一个符号。 ECC解码器被布置用于将码字解码为解码码字，并被设计为校正最大数量的错误。 该方法包括用于确定码字中的错误数量的错误检查步骤。 如果错误的数量大于ECC解码器可以校正的最大错误数，则执行第一符号修改步骤和第二符号修改步骤中的至少一个。 在第一符号修改步骤中，通过将符号的值增加到下一较高值电平来生成第一修改码字，并且在第二符号修改步骤中，通过将符号（Si）的值减小到第二修改码字来生成第二修改码字 下一个较低的值级别。 在分析步骤中，计算符号修改步骤的校正效果，并且在返回步骤中，基于校正效果或代码字的擦除来确定解码码字。

公开(公告)号：WO2012014140A2

公开(公告)日：2012-02-02

申请号：PCT/IB2011/053299

申请日：2011-07-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BUX, Werner ,  HAAS, Robert ,  HU, Xiaoyu ,  PLETKA, Roman, A.

Inventor： BUX, Werner ,  HAAS, Robert ,  HU, Xiaoyu ,  PLETKA, Roman, A.

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0848 ,  G06F12/0866 ,  G06F2212/214 ,  G06F2212/221 ,  G06F2212/222 ,  G06F2212/466 ,  G06F2212/7201

Abstract: The present idea provides a high read and write performance from/to a solid state memory device. The main memory (31) of the controller (1) is not blocked by a complete address mapping table covering the entire memory device (2). Instead such table is stored in the memory device (2) itself, and only selected portions of address mapping information are buffered in the main memory (31) in a read cache (311) and a write cache (312). A separation of the read cache (311) from the write cache (312) enables an address mapping entry being evictable from the read cache (311) without the need to update the related flash memory page storing such entry in the flash memory device (2). By this design, the read cache (311) may advantageously be stored on a DRAM even without power down protection, while the write cache (312) may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.

Abstract translation: 本想法提供了从/到固态存储器件的高读/写性能。 控制器（1）的主存储器（31）不被覆盖整个存储器件（2）的完整地址映射表阻塞。 相反，这样的表被存储在存储器件（2）本身中，并且只有地址映射信息的选择部分被缓存在读取高速缓存（311）和写入高速缓存（312）中的主存储器（31）中。 读取高速缓存（311）与写入高速缓存（312）的分离使得能够从读取的高速缓存（311）中消除地址映射条目，而不需要在闪存设备（2）中更新存储这样的条目的相关闪存页面 ）。 通过该设计，即使没有掉电保护，读高速缓存（311）也可有利地存储在DRAM上，而写高速缓存（312）可优选地被实现在非易失性或其他故障安全存储器中。 这导致了非易失性或故障安全存储器的总体配置的减少以及改进的可扩展性和性能。

公开(公告)号：WO2012001556A1

公开(公告)日：2012-01-05

申请号：PCT/IB2011/052492

申请日：2011-06-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CIDECIYAN, Roy, Daron ,  ELEFTHERIOU, Evangelos, S. ,  HAAS, Robert ,  HU, Xiaoyu ,  ILIADIS, Ilias ,  PLETKA, Roman, A.

Inventor： CIDECIYAN, Roy, Daron ,  ELEFTHERIOU, Evangelos, S. ,  HAAS, Robert ,  HU, Xiaoyu ,  ILIADIS, Ilias ,  PLETKA, Roman, A.

IPC: G11C16/34

CPC classification number: G06F12/0246 ,  G06F2212/7211 ,  G11C16/3495

Abstract: The invention is directed to a method for wear-leveling cells or pages or sub- pages or blocks of a memory such as a flash memory, the method comprising: - receiving (S10) a chunk of data to be written on a cell or page or sub-page or block of the memory; - counting (S40) in the received chunk of data the number of times a given type of binary data '0' or Ί ' is to be written; and - distributing (S50) the writing of the received chunk of data amongst cells or pages or sub-pages or blocks of the memory such as to wear-level the memory with respect to the number of the given type of binary data '0' or Ί ' counted in the chunk of data to be written.

Abstract translation: 本发明涉及一种用于对诸如闪速存储器之类的存储器的单元格或页面或子页面或块进行磨损均衡的方法，所述方法包括： - 接收（S10）要写入单元或页面的数据块 或子页或块的存储器; - 在接收到的数据块中计数（S40）次数给定类型的二进制数据“0”或？ “要写 以及 - 分配（S50）在存储器的单元格或页面或子页面或块之间写入所接收的数据块，以便相对于给定类型的二进制数据“0”的数量对存储器进行磨损级别 要么 ？ “在数据块中计算要写入。

公开(公告)号：WO2011067706A1

公开(公告)日：2011-06-09

申请号：PCT/IB2010/055471

申请日：2010-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ANTONAKOPOULOS, Theodore A. ,  CIDECIYAN, Roy D. ,  HU, Xiao-Yu ,  ILIADIS, Ilias ,  PLETKA, Roman A.

Inventor： ANTONAKOPOULOS, Theodore A. ,  CIDECIYAN, Roy D. ,  HU, Xiao-Yu ,  ILIADIS, Ilias ,  PLETKA, Roman A.

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F2212/7211

Abstract: A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non- uniform manner.

Abstract translation: 在具有多个存储单元的固态存储器内部进行具有多个存储单元的固态存储器内的块内损耗均衡的方法包括以非均匀方式写入多个存储单元中的至少某些存储单元的步骤， 在块内级别平衡固态存储器内的多个存储单元中的至少某些存储器单元的磨损。 例如，如果多个存储器单元中的至少一些存储器单元的行为没有被表征，则该方法可以包括表征多个存储器单元中的至少一些的行为，并写入多个存储器中的至少某些存储器 基于表征的行为，并且以非均匀的方式。