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公开(公告)号：WO2007027975A1
公开(公告)日：2007-03-08
申请号：PCT/US2006/034158
申请日：2006-08-31
Applicant: KEMET ELECTRONICS CORPORATION , PRYMAK, John, D.
Inventor： PRYMAK, John, D.
IPC: H01G2/16
Abstract: A fused or high ESR ceramic capacitor (101) for power applications has a fuse or resistor inserted between an end termination (102) and a terminal (202) for one set of alternating conductive plates (201) in the capacitor. The length and thickness of the fuse (407) allows adjustment of the current capability of the fail-open device which provides protection for the circuit in the event of short-circuiting, or the pattern created by the thick-film resistor application (405) defining the added ESR for the capacitor.
Abstract translation: 用于功率应用的熔断或高ESR陶瓷电容器（101）具有插入在电容器中的一组交替导电板（201）的端部端子（102）和端子（202）之间的熔丝或电阻器。 保险丝（407）的长度和厚度允许调节在短路的情况下为电路提供保护的故障开启装置的电流能力或由厚膜电阻器应用（405）产生的图案， 定义电容器增加的ESR。
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公开(公告)号：WO2006047771A1
公开(公告)日：2006-05-04
申请号：PCT/US2005/039211
申请日：2005-10-26
Applicant: KEMET ELECTRONICS CORPORATION , PRYMAK, John, D.
Inventor： PRYMAK, John, D.
IPC: H01G2/06
CPC classification number: H01G4/248 , H01G2/065 , H01G4/232 , H05K3/3436 , H05K3/3442 , H05K2201/0367 , H05K2201/0373 , H05K2201/09381 , H05K2201/2081 , Y02P70/613
Abstract: Larger ceramic chip capacitors (101) are reliably mounted with minimal risk of flexure induced cracking on circuit boards by adding termination extensions (602, 602') to one face of the capacitor and soldering across all or part of the extensions. A ball grid array is preferred.
Abstract translation: 通过向电容器的一面添加终端延伸部（602,602'）并焊接到全部或部分扩展部分上，可靠地安装较大的陶瓷片状电容器（101），具有最小的电路板上的弯曲引起的开裂风险。 优选球栅阵列。
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公开(公告)号：WO2008100940A1
公开(公告)日：2008-08-21
申请号：PCT/US2008/053730
申请日：2008-02-12
Applicant: KEMET ELECTRONICS CORPORATION , RANDALL, Michael S. , RENNER, Gary , PRYMAK, John D. , TAJUDDIN, Azizuddin
Inventor： RANDALL, Michael S. , RENNER, Gary , PRYMAK, John D. , TAJUDDIN, Azizuddin
CPC classification number: H01L23/50 , H01L23/642 , H01L2924/0002 , H01L2924/19103 , H01L2924/3011 , H01L2924/00
Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.
Abstract translation: 描述了一种电容式插入器，具有电容插入器的电子封装和具有电子封装的电子器件。 插入器具有第一平面和第二平面。 上连接的阵列位于第一平面上，相对的下连接在第二平面上，上连接的每个上连接与下连接的下连接之间具有传导路径。 提供至少一个馈电电容器。 电容器具有多个平行板，其间具有电介质。 至少一个第一外部终端与第一组交替平行板电接触，并且至少一个第二外部端接件与第二组交替的平行板电接触。 电容器安装在第一平面上，第一外部端子与第一上连接件直接电接触，第二外部端子与第二上连接件直接电接触。 至少一个上部连接，第一外部端接和第二外部端接布置成与公共元件的元件接触垫直接电接触。
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公开(公告)号：WO2004093107A3
公开(公告)日：2008-01-03
申请号：PCT/US2004011531
申请日：2004-04-15
Applicant: KEMET ELECTRONICS CORP , PRYMAK JOHN D , RANDALL MICHAEL S
Inventor： PRYMAK JOHN D , RANDALL MICHAEL S
Abstract: A multi-layer capacitor with reduced ESL and internal electrodes for same. The multi-layer capacitor comprises a monolithic capacitor body comprising first polarity external electrodes (7) and second polarity external electrodes (7') on an exterior of the body. A first internal electrode (1) comprises first diverging lead-out electrodes (3) in electrical contact with the first polarity external electrodes (7). A second internal electrode (1') comprises second diverging lead-out electrodes (3') in electrical contact with the second polarity external electrodes (7'). The first internal electrode (1) and the second internal electrode (1') are in parallel spaced-apart relationship with a dielectric therebetween.
Abstract translation: 具有减少的ESL和内部电极的多层电容器。 多层电容器包括单体电容器本体，其包括在主体外部的第一极性外部电极（7）和第二极性外部电极（7'）。 第一内部电极（1）包括与第一极性外部电极（7）电接触的第一发散引出电极（3）。 第二内部电极（1'）包括与第二极性外部电极（7'）电接触的第二发散引出电极（3'）。 第一内部电极（1）和第二内部电极（1'）与它们之间的电介质平行间隔开。
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公开(公告)号：WO2007075714A3
公开(公告)日：2007-12-21
申请号：PCT/US2006048472
申请日：2006-12-19
Applicant: MOTOROLA INC , KEMET ELECTRONICS CORP , DUNN GREGORY J , CHELINI REMY J , CROSWELL ROBERT T , LESSNER PHILIP M , PREVALLET MICHAEL D , PRYMAK JOHN D
Inventor： DUNN GREGORY J , CHELINI REMY J , CROSWELL ROBERT T , LESSNER PHILIP M , PREVALLET MICHAEL D , PRYMAK JOHN D
IPC: H01G9/00
CPC classification number: H01G9/045 , H01G9/0032 , H01G9/055 , H01G9/15 , H05K1/162 , H05K3/383 , H05K3/429 , H05K2201/0355 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718 , H05K2203/0315
Abstract: Embedded capacitors comprise a bimetal foil (500) that includes a first copper layer (205) and an aluminum layer (210) on the first copper layer. The aluminum layer has a smooth side adjacent the first copper layer and a high surface area textured side (215) opposite the first copper layer. The bimetal foil further includes an aluminum oxide layer (305) on the high surface area textured side of the aluminum layer, a conductive polymer layer (420) on the aluminum oxide layer, and a second copper layer (535) overlying the aluminum oxide layer. The bimetal foil may be embedded in a circuit board (700) to form high value embedded capacitors.
Abstract translation: 嵌入式电容器包括在第一铜层上包括第一铜层（205）和铝层（210）的双金属箔（500）。 铝层具有邻近第一铜层的平滑侧面和与第一铜层相对的高表面积纹理化侧面（215）。 双金属箔还包括在铝层的高表面积纹理化侧的氧化铝层（305），氧化铝层上的导电聚合物层（420）和覆盖氧化铝层的第二铜层（535） 。 双金属箔可以嵌入在电路板（700）中以形成高价值的嵌入式电容器。
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Patent Agency Ranking
公开(公告)号：WO2010045540A2
公开(公告)日：2010-04-22
申请号：PCT/US2009060982
申请日：2009-10-16
Applicant: KEMET ELECTRONICS CORP , PRYMAK JOHN D
Inventor： PRYMAK JOHN D
Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.
Abstract translation: 陶瓷多层表面贴装电容器具有固有的裂纹消除空间图案化，将柔性裂纹引导到安全区域，从而抵消任何电气故障。
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公开(公告)号：WO2008109283A1
公开(公告)日：2008-09-12
申请号：PCT/US2008/054906
申请日：2008-02-25
Applicant: KEMET ELECTRONICS CORPORATION , MOTOROLA, INC. , PRYMAK, John, D. , STOLARSKI, Chris , JACOBS, David , WAYNE, Chris , LESSNER, Philip , KINARD, John, T. , MELODY, Alethia , DUNN, Gregory , CROSWELL, Robert, T. , CHELINI, Remy, J.
Inventor： PRYMAK, John, D. , STOLARSKI, Chris , JACOBS, David , WAYNE, Chris , LESSNER, Philip , KINARD, John, T. , MELODY, Alethia , DUNN, Gregory , CROSWELL, Robert, T. , CHELINI, Remy, J.
CPC classification number: H01G9/0029 , H01G9/012 , H01G9/0425 , H01G9/055 , H01G9/15 , H05K1/185 , Y10T29/417
Abstract: An improved method for forming a capacitor. The method includes the steps of: providing a metal foil; forming a dielectric on the metal foil; applying a non-conductive polymer dam on the dielectric to isolate discrete regions of the dielectric; forming a cathode in at least one discrete region of the discrete regions on the dielectric; and cutting the metal foil at the non-conductive polymer dam to isolate at least one capacitor comprising one cathode, one discrete region of the dielectric and a portion of the metal foil with the discrete region of the dielectric.
Abstract translation: 一种形成电容器的改进方法。 该方法包括以下步骤：提供金属箔; 在金属箔上形成电介质; 将非导电聚合物坝施加在电介质上以隔离电介质的离散区域; 在电介质上的离散区域的至少一个离散区域中形成阴极; 并且在非导电聚合物阻挡件处切割金属箔以将包括一个阴极，电介质的一个离散区域和金属箔的一部分的至少一个电容器与电介质的离散区域隔离。
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公开(公告)号：WO2010045540A3
公开(公告)日：2010-04-22
申请号：PCT/US2009/060982
申请日：2009-10-16
Applicant: KEMET ELECTRONICS CORPORATION , PRYMAK, John D.
Inventor： PRYMAK, John D.
Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.
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公开(公告)号：WO2010014580A3
公开(公告)日：2010-04-15
申请号：PCT/US2009051919
申请日：2009-07-28
Applicant: KEMET ELECTRONICS CORP , MOTOROLA INC , PRYMAK JOHN D , STOLARSKI CHRIS , MELODY ALETHIA , CHACKO ANTONY P , DUNN GREGORY J
Inventor： PRYMAK JOHN D , STOLARSKI CHRIS , MELODY ALETHIA , CHACKO ANTONY P , DUNN GREGORY J
CPC classification number: H05K1/162 , H01G9/012 , H01G9/042 , H01G9/045 , H01G9/15 , H05K3/429 , H05K2201/0329 , H05K2201/0355 , H05K2201/09509 , H05K2201/09763 , H05K2201/09909 , H05K2203/0315 , Y10T29/417 , Y10T29/435
Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
Abstract translation: 一种用于形成具有电容的层压体的方法和由此形成的层压体。 该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。 在电介质上形成导电层。 处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。 在导电层和阴极迹线之间形成阴极导电耦合，并且在导电箔和阳极迹线之间形成阳极导电耦合。
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公开(公告)号：WO2010014580A2
公开(公告)日：2010-02-04
申请号：PCT/US2009/051919
申请日：2009-07-28
Applicant: KEMET ELECTRONICS CORPORATION , MOTOROLA, INC. , PRYMAK, John, D. , STOLARSKI, Chris , MELODY, Alethia , CHACKO, Antony, P. , DUNN, Gregory, J.
Inventor： PRYMAK, John, D. , STOLARSKI, Chris , MELODY, Alethia , CHACKO, Antony, P. , DUNN, Gregory, J.
CPC classification number: H05K1/162 , H01G9/012 , H01G9/042 , H01G9/045 , H01G9/15 , H05K3/429 , H05K2201/0329 , H05K2201/0355 , H05K2201/09509 , H05K2201/09763 , H05K2201/09909 , H05K2203/0315 , Y10T29/417 , Y10T29/435
Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
Abstract translation: 用于形成具有电容的层压体的方法和由此形成的层压体。 该方法包括提供衬底和在衬底上层压导电箔的步骤，其中箔具有电介质。 在电介质上形成导电层。 处理导电箔以将包含导电层的导电箔的区域与附加的导电箔电隔离。 在导电层和阴极迹线之间形成阴极导电偶，并且在导电箔和阳极迹线之间形成阳极导电偶。
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