公开(公告)号：WO2006116534A2

公开(公告)日：2006-11-02

申请号：PCT/US2006/015882

申请日：2006-04-26

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. ,  KUEKES, Phillip, J. ,  ROBINETT, Warren, J. ,  SEROUSSI, Gadiel ,  WILLIAMS, R., Stanley

Inventor： KUEKES, Phillip, J. ,  ROBINETT, Warren, J. ,  SEROUSSI, Gadiel ,  WILLIAMS, R., Stanley

IPC: G06F11/10 ,  G11C8/10 ,  G11C8/20 ,  G11C13/00

CPC classification number: G11C13/0023 ,  B82Y10/00 ,  G06F11/1016 ,  G11C8/10 ,  G11C11/54 ,  G11C13/0002 ,  G11C2213/77 ,  G11C2213/81

Abstract: One embodiment of the present invention provides a demultiplexer implemented as a nonowire crossbar (3000) or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines (3003, 3004) to 2 k or fewer nanowires (3006-3009), employing supplemental, internal address lines (3010, 3012) to map 2 k nanowire addresses to a larger, internal, n -bit address space, where n > k . A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2 k nanowires, with n > k , using 2 k , well-distributed, n -bit external addresses to access the 2 k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire address to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.

Abstract translation: 本发明的一个实施例提供了实现为非线性横杆（3000）或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关的解复用器。 一个实施例的解复用器将使用补充的内部地址线（3010,3012）的k个微米地址线（3003,3004）上输入的信号解复用到更少的纳米线（3006-3009） 将2nm的纳米线地址映射到更大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例提供了在n个微米级地址线上输入的信号到n≥k的二极管，使用2分布良好的分布， n位外部地址以访问2nm的纳米线。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。

公开(公告)号：WO2007030208A1

公开(公告)日：2007-03-15

申请号：PCT/US2006/028300

申请日：2006-07-21

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L. P. ,  KUEKES, Philip, J. ,  ROBINETT, Warren, J. ,  ROTH, Ron, M. ,  SEROISSI, Gadiel ,  SNIDER, Gregory, S. ,  WILLIAMS, R., Stanley

Inventor： KUEKES, Philip, J. ,  ROBINETT, Warren, J. ,  ROTH, Ron, M. ,  SEROISSI, Gadiel ,  SNIDER, Gregory, S. ,  WILLIAMS, R., Stanley

IPC: G11C13/00 ,  G11C8/10

CPC classification number: G11C8/10 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/77 ,  G11C2213/81

Abstract: Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing schemes for reliably addressing nanowire-junctions within nanowire crossbars (1700). The addressing schemes allow for change in the resistance state, or other physical or electronic state, of a selected nanowire-crossbar junction without changing the resistance state, or other physical or electronic state, of the remaining nanowire-crosbar junctions, and without destruction of either the selected nanowire-crossbar junction or the remaining, non-selected nanowire-crossbar junctions. Additional embodiments of the present invention included nanoscale memory arrays (1700) and other nanoscale electronic devices that incorporate the nanowire-addressing-scheme embodiments of the present invention. Certain of the embodiments of the present invention employ constant-weight codes (1308), a well-known class or error-control-encoding codes, as addressed-nanowire selection voltages applied to microscale output signal lines (1316-1319) of microscale/nanoscale encoder-demultiplexers that are selectively interconnected with a set of nanowires (1310-1315).

Abstract translation: 本发明的各种实施例包括用于确定纳米线寻址方案的方法，并且包括微纳米级纳米级电子器件，其纳入用于在纳米线交叉梁内可靠地寻址纳米线结的纳米线寻址方案（1700）。 寻址方案允许选择的纳米线 - 交叉连接点的电阻状态或其他物理或电子状态的改变，而不改变剩余的纳米线 - 交叉连接点的电阻状态或其他物理或电子状态，并且不破坏 选择的纳米线 - 交叉结或剩余的未选择的纳米线 - 交叉点结。 本发明的另外的实施例包括纳米尺度存储器阵列（1700）和纳入本发明的纳米线寻址方案实施例的其它纳米级电子器件。 本发明的某些实施例采用公知的类或误差控制编码代码（1308）作为施加到微米级/微米级编码的微米级输出信号线（1316-1319）的寻址纳米线选择电压， 纳米级编码器 - 解复用器，其选择性地与一组纳米线相互连接（1310-1315）。

公开(公告)号：WO2006116534A3

公开(公告)日：2007-02-15

申请号：PCT/US2006015882

申请日：2006-04-26

Applicant: HEWLETT PACKARD DEVELOPMENT CO ,  KUEKES PHILLIP J ,  ROBINETT WARREN J ,  SEROUSSI GADIEL ,  WILLIAMS R STANLEY

Inventor： KUEKES PHILLIP J ,  ROBINETT WARREN J ,  SEROUSSI GADIEL ,  WILLIAMS R STANLEY

IPC: G06F11/10 ,  G11C8/10 ,  G11C8/20 ,  G11C13/00

CPC classification number: G11C13/0023 ,  B82Y10/00 ,  G06F11/1016 ,  G11C8/10 ,  G11C11/54 ,  G11C13/0002 ,  G11C2213/77 ,  G11C2213/81

Abstract: One embodiment of the present invention provides a demultiplexer implemented as a nonowire crossbar (3000) or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines (3003, 3004) to 2 k or fewer nanowires (3006-3009), employing supplemental, internal address lines (3010, 3012) to map 2 k nanowire addresses to a larger, internal, n-bit address space, where n > k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2 k nanowires, with n > k, using 2 k , well-distributed, n-bit external addresses to access the 2 k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire address to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.

Abstract translation: 本发明的一个实施例提供了一种解复用器，其实现为非线性横杆（3000）或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关。 一个实施例的解复用器使用补充的内部地址线（3010,3012）将在k个微米地址线（3003,3004）上输入的信号解复用到更少的纳米线（3006-3009） 将2nm的纳米线地址映射到更大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例提供了在n个微米级地址线上输入的信号，其中n≥k，使用2分布良好的二极管， n位外部地址以访问2nm的纳米线。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。