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    MULTIPLEXER INTERFACE TO A NANOSCALE-CROSSBAR
    1.
    发明申请
    MULTIPLEXER INTERFACE TO A NANOSCALE-CROSSBAR 审中-公开
    多功能接口到纳斯卡尔 - 交叉杆

    公开(公告)号：WO2006115980A1

    公开(公告)日：2006-11-02

    申请号：PCT/US2006/014888

    申请日：2006-04-19

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L. P. ,  KUEKES, Phillip, J. ,  WILLIAMS, Stanley, R.

    Inventor： KUEKES, Phillip, J. ,  WILLIAMS, Stanley, R.

    IPC: G11C13/02

    CPC classification number: G11C8/10 ,  B82Y10/00 ,  G11C13/0023 ,  G11C13/02 ,  G11C2213/77 ,  G11C2213/81 ,  Y10S977/938

    Abstract: Various embodiments of the present invention are directed to electronic means for reading the content of a nanowire-crossbar memory. In one embodiment of the present invention, a microscale or sub-microscale signal line (402) is interconnected with one set of parallel nanowires (310-315) emanating from a nanowire-crossbar memory by configurable, nanowire-junction switches (404). The microscale or sub-microscale signal line (402) serves as a single-wire multiplexer, allowing the contents of any particular single-bit atorage element (316) within the nanowire-crossbar memory to be read.

    Abstract translation: 本发明的各种实施例涉及用于读取纳米线交叉存储器的内容的电子装置。 在本发明的一个实施例中，微米级或亚微米级信号线（402）与通过可配置的纳米线结开关（404）从纳米线交叉存储器发出的一组平行纳米线（310-315）互连。 微尺度或亚微米信号线（402）用作单线多路复用器，允许读取纳米线交叉存储器内的任何特定单位位元件（316）的内容。

    NANOSCALE INTERCONNECTION INTERFACE
    3.
    发明申请
    NANOSCALE INTERCONNECTION INTERFACE 审中-公开
    纳米互连接口

    公开(公告)号：WO2006116534A2

    公开(公告)日：2006-11-02

    申请号：PCT/US2006/015882

    申请日：2006-04-26

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. ,  KUEKES, Phillip, J. ,  ROBINETT, Warren, J. ,  SEROUSSI, Gadiel ,  WILLIAMS, R., Stanley

    Inventor： KUEKES, Phillip, J. ,  ROBINETT, Warren, J. ,  SEROUSSI, Gadiel ,  WILLIAMS, R., Stanley

    IPC: G06F11/10 ,  G11C8/10 ,  G11C8/20 ,  G11C13/00

    CPC classification number: G11C13/0023 ,  B82Y10/00 ,  G06F11/1016 ,  G11C8/10 ,  G11C11/54 ,  G11C13/0002 ,  G11C2213/77 ,  G11C2213/81

    Abstract: One embodiment of the present invention provides a demultiplexer implemented as a nonowire crossbar (3000) or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines (3003, 3004) to 2 k or fewer nanowires (3006-3009), employing supplemental, internal address lines (3010, 3012) to map 2 k nanowire addresses to a larger, internal, n -bit address space, where n > k . A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2 k nanowires, with n > k , using 2 k , well-distributed, n -bit external addresses to access the 2 k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire address to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.

    Abstract translation: 本发明的一个实施例提供了实现为非线性横杆（3000）或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关的解复用器。 一个实施例的解复用器将使用补充的内部地址线（3010,3012）的k个微米地址线（3003,3004）上输入的信号解复用到更少的纳米线（3006-3009） 将2nm的纳米线地址映射到更大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例提供了在n个微米级地址线上输入的信号到n≥k的二极管，使用2分布良好的分布， n位外部地址以访问2nm的纳米线。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。

    THREE-DIMENSIONAL NANOSCALE CROSSBARS
    4.
    发明申请
    THREE-DIMENSIONAL NANOSCALE CROSSBARS 审中-公开
    三维NANOSCALE十字架

    公开(公告)号：WO2006116552A1

    公开(公告)日：2006-11-02

    申请号：PCT/US2006/015933

    申请日：2006-04-25

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. ,  WILLIAMS, R., Stanley ,  KUEKES, Phillip, J.

    Inventor： WILLIAMS, R., Stanley ,  KUEKES, Phillip, J.

    IPC: G11C13/02

    CPC classification number: H04L49/40 ,  B82Y10/00 ,  G11C13/02 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/81 ,  H04L49/101 ,  Y10S977/762 ,  Y10S977/767

    Abstract: Various embodiments of the present invention include three-dimensional, at least partially nanoscale, electronic circuits and devices in which signals can be routed (1016) in three independent directions, and in which electronic components can be fabricated at junctions (510, 802) interconnected by internal signal lines ( 502-509 and 702-709). The three-dimensional, at least partially nanoscale, electronic circuits and devices include layers, the nanowire or microscale-or-submicroscale/nanowire junctions of each of which may be economically and efficiently fabricated as one type of electronic component. Various embodiments of the present invention include nanoscale memories, nanoscale programmable arrays, nanoscale multiplexers and demultiplexers, and an almost limitless number of specialized nanoscale circuits and nanoscale electronic components.

    Abstract translation: 本发明的各种实施例包括三维，至少部分地纳米尺度的电子电路和装置，其中信号可以在三个独立的方向上被路由（1016），并且其中电子部件可以在互连的连接（510,802）处制造 通过内部信号线（502-509和702-709）。 三维，至少部分纳米级的电子电路和器件包括层，其中每一个的纳米线或微米级或亚微米级/纳米线结可以经济地和有效地制造为一种类型的电子部件。 本发明的各种实施例包括纳米级存储器，纳米尺度可编程阵列，纳米级多路复用器和解复用器，以及几乎无限数量的专用纳米尺度电路和纳米级电子部件。

    ACTIVE INTERCONNECTS AND CONTROL POINTS IN INTEGRATED CIRCUITS
    6.
    发明申请
    ACTIVE INTERCONNECTS AND CONTROL POINTS IN INTEGRATED CIRCUITS 审中-公开
    集成电路中的主动互连和控制点

    公开(公告)号：WO2006115968A3

    公开(公告)日：2007-08-16

    申请号：PCT/US2006014856

    申请日：2006-04-19

    Applicant: HEWLETT PACKARD DEVELOPMENT CO ,  WILLIAMS R STANLEY ,  KUEKES PHILLIP J ,  PERNER FREDERICK A ,  SNIDER GREGORY S ,  STEWART DUNCAN

    Inventor： WILLIAMS R STANLEY ,  KUEKES PHILLIP J ,  PERNER FREDERICK A ,  SNIDER GREGORY S ,  STEWART DUNCAN

    IPC: H01L21/66

    CPC classification number: H05K7/1092 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In various embodiments of the present invention, tunable resistors (1102) are introduced at the interconnect layer of the integrated circuits (102) in order to provide a means for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronics characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors (1102) included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains. In some cases, components and modules may be turned off, while, in other cases, components and modules may be turned on.

    Abstract translation: 在本发明的各种实施例中，可调谐电阻器（1102）被引入集成电路（102）的互连层，以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或 配置后续制造的集成电路。 例如，当某些内部组件（例如晶体管）由于制造缺陷而没有指定的电子特性时，根据本发明的实施例调整包括在集成电路的互连层中的可调电阻器（1102）的可变电阻 可以用于调整内部电压和/或电平，以改善有缺陷的部件。 在其他情况下，可调谐电阻器可以用作开关以配置集成电路部件，包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。 在某些情况下，可能会关闭组件和模块，而在其他情况下，可能会打开组件和模块。

    ACTIVE INTERCONNECTS AND CONTROL POINTS IN INTEGRATED CIRCUITS
    7.
    发明申请
    ACTIVE INTERCONNECTS AND CONTROL POINTS IN INTEGRATED CIRCUITS 审中-公开
    集成电路中的主动互连和控制点

    公开(公告)号：WO2006115968A2

    公开(公告)日：2006-11-02

    申请号：PCT/US2006/014856

    申请日：2006-04-19

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. ,  WILLIAMS, R., Stanley ,  KUEKES, Phillip, J. ,  PERNER, Frederick, A. ,  SNIDER, Gregory, S. ,  STEWART, Duncan

    Inventor： WILLIAMS, R., Stanley ,  KUEKES, Phillip, J. ,  PERNER, Frederick, A. ,  SNIDER, Gregory, S. ,  STEWART, Duncan

    IPC: H01L21/66

    CPC classification number: H05K7/1092 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In various embodiments of the present invention, tunable resistors (1102) are introduced at the interconnect layer of the integrated circuits (102) in order to provide a means for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronics characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors (1102) included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains. In some cases, components and modules may be turned off, while, in other cases, components and modules may be turned on.

    Abstract translation: 在本发明的各种实施例中，可调谐电阻器（1102）被引入集成电路（102）的互连层，以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或 配置后续制造的集成电路。 例如，当诸如晶体管的某些内部部件由于制造缺陷而没有指定的电子特性时，根据本发明的实施例调整包括在集成电路的互连层中的可调电阻器（1102）的可变电阻 可以用于调整内部电压和/或电平，以改善有缺陷的部件。 在其他情况下，可调谐电阻器可以用作开关来配置集成电路组件，包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。 在某些情况下，可能会关闭组件和模块，而在其他情况下，可能会打开组件和模块。

    NANOSCALE INTERCONNECTION INTERFACE
    9.
    发明申请
    NANOSCALE INTERCONNECTION INTERFACE 审中-公开
    纳米互连接口

    公开(公告)号：WO2006116534A3

    公开(公告)日：2007-02-15

    申请号：PCT/US2006015882

    申请日：2006-04-26

    Applicant: HEWLETT PACKARD DEVELOPMENT CO ,  KUEKES PHILLIP J ,  ROBINETT WARREN J ,  SEROUSSI GADIEL ,  WILLIAMS R STANLEY

    Inventor： KUEKES PHILLIP J ,  ROBINETT WARREN J ,  SEROUSSI GADIEL ,  WILLIAMS R STANLEY

    IPC: G06F11/10 ,  G11C8/10 ,  G11C8/20 ,  G11C13/00

    CPC classification number: G11C13/0023 ,  B82Y10/00 ,  G06F11/1016 ,  G11C8/10 ,  G11C11/54 ,  G11C13/0002 ,  G11C2213/77 ,  G11C2213/81

    Abstract: One embodiment of the present invention provides a demultiplexer implemented as a nonowire crossbar (3000) or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines (3003, 3004) to 2 k or fewer nanowires (3006-3009), employing supplemental, internal address lines (3010, 3012) to map 2 k nanowire addresses to a larger, internal, n-bit address space, where n > k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2 k nanowires, with n > k, using 2 k , well-distributed, n-bit external addresses to access the 2 k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire address to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.

    Abstract translation: 本发明的一个实施例提供了一种解复用器，其实现为非线性横杆（3000）或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关。 一个实施例的解复用器使用补充的内部地址线（3010,3012）将在k个微米地址线（3003,3004）上输入的信号解复用到更少的纳米线（3006-3009） 将2nm的纳米线地址映射到更大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例提供了在n个微米级地址线上输入的信号，其中n≥k，使用2分布良好的二极管， n位外部地址以访问2nm的纳米线。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。

    SCALABLE, COMPONENT-ACCESSIBLE, AND HIGHLY INTERCONNECTED THREE-DIMENSIONAL COMPONENT ARRANGEMENT WITHIN A SYSTEM
    10.
    发明申请
    SCALABLE, COMPONENT-ACCESSIBLE, AND HIGHLY INTERCONNECTED THREE-DIMENSIONAL COMPONENT ARRANGEMENT WITHIN A SYSTEM 审中-公开
    在系统中可扩展，组件可访问性和高度互连的三维组件布置

    公开(公告)号：WO2006028845A1

    公开(公告)日：2006-03-16

    申请号：PCT/US2005/030966

    申请日：2005-08-30

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L. P. ,  KUEKES, Phillip, J. ,  WILLIAMS, R., Stanley, ,  BEAUSOLEIL, Raymond, G.

    Inventor： KUEKES, Phillip, J. ,  WILLIAMS, R., Stanley, ,  BEAUSOLEIL, Raymond, G.

    IPC: G06F1/18

    CPC classification number: G06F1/18 ,  G06F17/509 ,  H05K7/1444

    Abstract: Embodiments of the present invention include dense, but assessible and well-interconnected component arrangements within multi-component systems, such as high-end multi-processor computer systems, and methods for constructing such arrangements. In a described embodiment, integrated-circuit-containing processing components, referred to as a "flat components" (202, 206), are arranged into local blocks (400) of intercommunicating flat components. The local flat-component blocks are arranged into interconnected, primitive multi-block repeating units (700), and the primitive local-block repeating units are layered togehter in a three-dimensional, regularly repeating structure that can be assembled to approximately fill any specified three-dimensional volume (Figure 9). The arrangement provides for relatively short, direct pathways (1312-1320) from the surface of the specificed volume to any particular local block component within the three-dimensional arrangement.

    Abstract translation: 本发明的实施例包括诸如高端多处理器计算机系统的多组件系统内的密集但可评估和良好互连的部件布置，以及用于构造这种布置的方法。 在所描述的实施例中，被称为“平坦部件”（202,206）的集成电路的处理部件被布置在相互连通的平面部件的局部块（400）中。 本地平面组件块被布置成互连的原始多块重复单元（700），并且原始局部块重复单元以三维的规则重复结构分层成形，可以组装成大致填充任何指定的 三维体积（图9）。 该装置提供从特定体积的表面到三维排列中的任何特定局部块分量的相对短的直接通路（1312-1320）。

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