公开(公告)号：WO2013095518A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066891

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S. ,  RUFF, Klaus J. ,  VERGIS, George ,  SAH, Suneeta

Inventor： BAINS, Kuljit S. ,  RUFF, Klaus J. ,  VERGIS, George ,  SAH, Suneeta

IPC: G06F12/00 ,  G06F11/10 ,  G06F13/14

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0787 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1612 ,  G06F13/16 ,  G06F13/28 ,  G11C7/1006 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

Abstract translation: 通过将数据通过地址总线传送到连接到数据总线的设备来读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。 寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。 主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。 然后主机处理器从存储器件的寄存器读取信息。

公开(公告)号：WO2013109284A1

公开(公告)日：2013-07-25

申请号：PCT/US2012/021988

申请日：2012-01-20

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S. ,  SAH, Suneeta

Inventor： BAINS, Kuljit S. ,  SAH, Suneeta

IPC: G11C11/409 ,  G06F12/00

CPC classification number: G11C7/1072 ,  G11C11/4076

Abstract: Embodiments of an apparatus, system and method for using Per DRAM Addressability (PDA) to program Multi-Purpose Registers (MPRs) of a dynamic random access memory (DRAM) device are described herein. Embodiments of the invention allow unique 32 bit patterns to be stored for each DRAM device on a rank, thereby enabling data bus training to be done in parallel. Furthermore, embodiments of the invention provide 32 bits of storage per DRAM device on a rank for the system BIOS for storing codes such as MR values, or for any other purpose (e.g., temporary scratch storage to be used by BIOS processes).

Abstract translation: 本文描述了使用每DRAM可寻址性（PDA）来编程动态随机存取存储器（DRAM）设备的多用途寄存器（MPR）的装置，系统和方法的实施例。 本发明的实施例允许为等级上的每个DRAM设备存储唯一的32位模式，从而使数据总线训练能够并行完成。 此外，本发明的实施例在用于存储诸如MR值的代码或用于任何其它目的（例如，由BIOS处理使用的临时暂存）的系统BIOS的等级上为每个DRAM设备提供32位存储。