公开(公告)号：WO2019173296A1

公开(公告)日：2019-09-12

申请号：PCT/US2019/020695

申请日：2019-03-05

Applicant: SEMTECH CORPORATION

Inventor： CHANG, Chin ,  CHEN, Woody

IPC: H05B37/02 ,  H02J9/02 ,  H02H3/20

Abstract: A circuit comprising a first regulator coupled to a voltage input, a second regulator coupled to a voltage output and a switch coupled to the first regulator and the second regulator, wherein the switch is configured to provide voltage to a load from the voltage input when the voltage input is greater than a first predetermined voltage, and to provide voltage to the load from the voltage output when the voltage input is lower than a second predetermined voltage.

公开(公告)号：WO2019055956A1

公开(公告)日：2019-03-21

申请号：PCT/US2018/051420

申请日：2018-09-18

Applicant: SEMTECH CORPORATION

Inventor： TEGGATZ, Ross, E. ,  BALDWIN, David, John ,  BLACKALL, Eric, Christian ,  HOU, Feng ,  CAI, Wen ,  STINGU, Emanuel

IPC: H02J7/00 ,  B60L11/18 ,  H02J50/12 ,  H02J50/80 ,  H01M10/42

Abstract: A system is disclosed that includes a wireless power receiver, a battery charging system coupled to the wireless power receiver and configured to charge a battery using power received from the wireless power receiver and a wireless data communication system coupled to the wireless power receiver and the battery charging system, the wireless data communication system configured to determine a power requirement and to transmit the power requirement using the wireless power receiver.

公开(公告)号：WO2014074238A1

公开(公告)日：2014-05-15

申请号：PCT/US2013/061554

申请日：2013-09-25

Applicant: SEMTECH CORPORATION

Inventor： NYS, Olivier ,  KRUMMENACHER, Francois

IPC: G01R17/00 ,  G01R1/30

CPC classification number: H03F1/52 ,  H03F1/3211 ,  H03F3/3022 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45645 ,  H03F3/45941 ,  H03F3/45973 ,  H03F2200/261 ,  H03F2203/45082 ,  H03F2203/45138 ,  H03F2203/45431 ,  H03F2203/45434 ,  H03F2203/45441 ,  H03F2203/45528

Abstract: A system and method for adjusting a common mode output voltage in an instrumentation amplifier is provided. In one aspect, the common mode output voltage is increased or decreased with respect to the common mode input voltage to enable high amplification of the signal input to the instrumentation amplifier. Moreover, the common mode output voltage can be driven to (or approximately to) a target voltage value such as, but not limited to, half the supply, even if the common mode input voltage is close to supply or ground rail voltage. Thus, a high amplification of the differential input voltage can be obtained and utilized for various applications requiring rail to rail input.

Abstract translation: 提供了一种用于调整仪表放大器中的共模输出电压的系统和方法。 在一个方面，共模输出电压相对于共模输入电压增加或减小，以便能够对输入到仪表放大器的信号进行高放大。 此外，即使共模输入电压接近电源或接地电压，共模输出电压也可被驱动到（或近似）目标电压值，例如但不限于电源的一半。 因此，可以获得差分输入电压的高放大率并且用于需要轨对轨输入的各种应用。

公开(公告)号：WO2012099993A3

公开(公告)日：2012-07-26

申请号：PCT/US2012/021768

申请日：2012-02-15

Applicant: SEMTECH CORPORATION ,  MONNEY, Pascal

Inventor： MONNEY, Pascal

IPC: G06F3/044

Abstract: A capacitive touch sensor and LED driver device achieves a reduction in pin count by multiplexing LED drive functionality and capacitive sense functionality on each input / output pin. A control circuit switches between LED drive mode and capacitive sense mode at a frequency of approximately 200 Hz, although other switching frequencies can be used. A bias driver functions as a current sink for LEDs in LED drive mode and can also be used to drive a bias voltage to the LEDs during capacitive sense mode to improve noise immunity.

公开(公告)号：WO2020081448A1

公开(公告)日：2020-04-23

申请号：PCT/US2019/056109

申请日：2019-10-14

Applicant: SEMTECH CORPORATION

Inventor： COURTNEY, David, Francis ,  GARZA, Angel Mario, Cano

IPC: H01L23/492 ,  H01L23/00

Abstract: A circuit, comprising a diode, a conductive upper support disposed on top of the diode and electrically coupled to the diode, a conductive lower support disposed underneath the diode and electrically coupled to the diode, a mechanical support disposed adjacent to the diode, the conductive upper support and the conductive lower support, an insulator disposed underneath the mechanical support, an upper terminal coupled to the mechanical support and electrically coupled to the conductive upper support and a lower terminal coupled to the insulator and electrically coupled to the conductive lower support.

公开(公告)号：WO2014062381A2

公开(公告)日：2014-04-24

申请号：PCT/US2013/063026

申请日：2013-10-02

Applicant: SEMTECH CORPORATION ,  AEBISCHER, Daniel ,  CHEVROULET, Michel

Inventor： AEBISCHER, Daniel ,  CHEVROULET, Michel

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L21/823892 ,  H01L27/0921 ,  H02M3/073 ,  H02M2003/078

Abstract: A charge pump circuit includes a substrate and first well region formed in the substrate. A first transistor includes first and second conduction regions disposed in the first well region. A second well region is formed in the substrate. A third well region is formed within the second well region. A second transistor includes first and second conduction regions disposed in the third well region. The second well region and third well region are coupled to a common terminal. The common terminal receives a local potential and the first well region and second well region are commonly maintained at the local potential. The first transistor and second transistor operate within the charge pump cell. A plurality of charge pump cells can be cascaded together with an output of a first charge pump cell coupled to an input of a second charge pump cell.

Abstract translation: 电荷泵电路包括基板和形成在基板中的第一阱区域。 第一晶体管包括设置在第一阱区中的第一和第二导电区。 在衬底中形成第二阱区。 第三阱区形成在第二阱区内。 第二晶体管包括设置在第三阱区中的第一和第二导电区域。 第二阱区域和第三阱区域耦合到公共端子。 公共端子接收局部电位，并且第一阱区域和第二阱区域通常保持在局部电位。 第一晶体管和第二晶体管在电荷泵单元内工作。 多个电荷泵电池可以与耦合到第二电荷泵电池的输入的第一电荷泵电池的输出级联在一起。

公开(公告)号：WO2013148578A1

公开(公告)日：2013-10-03

申请号：PCT/US2013/033712

申请日：2013-03-25

Applicant: SEMTECH CORPORATION ,  VANDEL, Eric

Inventor： VANDEL, Eric

IPC: H04K1/10

CPC classification number: H03K17/007 ,  H03K17/693 ,  H03K2217/0054

Abstract: Described herein is a low-voltage multi-stage interleaver. The interleaver includes at least a first interleaver stage and a second interleaver stage. The first interleaver stage is either blocked or operating in a saturation region. The first interleaver stage facilitates cancellation of DC current, including a biasing current, so that the second interleaver stage receives no DC current input. The second interleaver stage is either blocked or operating in a linear region to allow the second interleaver stage to act as a passive current switch.

Abstract translation: 这里描述的是低电压多级交织器。 交织器至少包括第一交织器级和第二交织器级。 第一交错器级被阻塞或在饱和区域中操作。 第一交织器级促进DC电流的消除，包括偏置电流，使得第二交织器级不接收直流电流输入。 第二交织器级被阻塞或在线性区域中操作以允许第二交织器级用作无源电流开关。

公开(公告)号：WO2006026063A3

公开(公告)日：2006-03-09

申请号：PCT/US2005/027830

申请日：2005-08-05

Applicant: SEMTECH CORPORATION ,  LOU, Perry, W.

Inventor： LOU, Perry, W.

IPC: H03K19/003

Abstract: An adaptive output driver circuit utilizes an initial point matched impedance model to match the impedance of an output driver to the transmission line and produce an initial step voltage into the transmission line that is half of the desired final voltage. The driver output impedance is controlled by comparing a model of the actual working output stage to a target resistance given by the user. Control signals used to calibrate the impedance of the model to match the target are also used to adjust the working output buffer, so that when the impedance of the model matches the target, the impedance of the working buffer also matches the target impedance.

公开(公告)号：WO2003096036A1

公开(公告)日：2003-11-20

申请号：PCT/US2003/012959

申请日：2003-04-28

Applicant: SEMTECH CORPORATION ,  HEJDEMAN, Carl ,  MARTEN, Victor ,  MCKNIGHT, Andrew

Inventor： HEJDEMAN, Carl ,  MARTEN, Victor ,  MCKNIGHT, Andrew

IPC: G01R31/08

CPC classification number: H04L12/40039 ,  H04L7/0331 ,  H04L7/044 ,  H04L12/403

Abstract: A single-wire serial communications bus has a master device and one or more slave devices. The slave devices are addressed according to a predetermined addressing scheme in an address space. The master device starts a transmission with a number of line state changes which define a clock period to be used by the slave devices in clocking and framing the serial data. This permits omitting a clock line, thus saving a pin and saving printed circuit board space. This also permits the slave devices to shut down their own clocks during periods of inactivity on the bus, thus saving power. Likewise the master device is able to shut down its clock during periods of bus inactivity.

Abstract translation: 单线串行通信总线具有主设备和一个或多个从设备。 根据地址空间中的预定寻址方案寻址从设备。 主设备启动具有多个线路状态改变的传输，该线路状态改变定义了从设备在对串行数据进行定时和成帧时使用的时钟周期。 这允许省略时钟线，从而节省引脚并节省印刷电路板空间。 这也允许从设备在总线不活动期间关闭自己的时钟，从而节省电力。 同样，主器件能够在总线不活动期间关闭其时钟。

公开(公告)号：WO1997002606A1

公开(公告)日：1997-01-23

申请号：PCT/US1996008545

申请日：1996-06-03

Applicant: SEMTECH CORPORATION

Inventor： SEMTECH CORPORATION ,  YU, Bin ,  HU, Chenming ,  KING, Ya-Chin ,  POHLMAN, Jeffrey, T. ,  TRIVEDI, Rita

IPC: H01L29/861

CPC classification number: H01L29/8618 ,  H01L29/861 ,  H01L29/866

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characterisics. The punch-through diode includes a first region comprising an n+ region (12), a second region comprising a p- region abutting the first region, a third region comprising a p+ region (16) abutting the second region, and a fourth region comprising an n+ region (18) abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm , the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm and about 1.0E17 cm . The junction depth of the fourth (n+) region (18) should be greater than about 0.3 um. The thickness of the third (p+) region (16) should be between about 0.3 um and about 2.0 um, and the thickness of the second (p-) region should be between about 0.5 um and about 5.0 um.

Abstract translation: 穿通二极管瞬变抑制器件具有改变掺杂浓度的基极区域，以改善泄漏和夹紧特性。 穿通二极管包括包括n +区域（12）的第一区域，包括邻接第一区域的p-区域的第二区域，包括邻接第二区域的p +区域（16）的第三区域，以及包括 与第三区域邻接的n +区域（18）。 n +层的峰值掺杂剂浓度应为约1.5E18 cm 3，p +层的峰值掺杂浓度应在n +层的峰值浓度的约1至约5倍之间，p的掺杂浓度 - 层应在约0.5E14cm 3和约1.0E17cm 3之间。 第四（n +）区域（18）的结深度应该大于约0.3μm。 第三（p +）区域（16）的厚度应在约0.3μm至约2.0μm之间，并且第二（p-）区域的厚度应在约0.5μm至约5.0μm之间。