公开(公告)号：WO2014202641A1

公开(公告)日：2014-12-24

申请号：PCT/EP2014/062777

申请日：2014-06-17

Applicant: ST-ERICSSON SA

Inventor： KOLI, Kimmo

IPC: H04L25/02

CPC classification number: H04L25/4917 ,  H04B7/06 ,  H04L7/0079 ,  H04L25/0272 ,  H04L25/0292

Abstract: A receiver (100) for a three-wire digital interface, comprises a first resistive element (R1) coupled between a first input terminal (A) and a first junction node (JA), a second resistive element (R2) coupled between a second input terminal (B) and a second junction node (JB), and a third resistive element (R3) coupled between a third input terminal (C) and a third junction node (JC). A network (70) comprising first second and third network terminals (71, 72, 73) is coupled to, respectively, first, second and third junction nodes (JA, JB, JC). The network has substantially the same impedance between all pairs of the first, second and third network terminals. A first comparator (C1) has a non-inverting input (10) coupled to the first input terminal (A), an inverting input (12) coupled to the second junction node (JB), and an output (14) coupled to a first output terminal (AJ). A second comparator (C2) has a non-inverting input (20) coupled to the first input terminal (A), an inverting input (22) coupled to the third junction node (JC), and an output (24) coupled to a second output terminal (AK). A third comparator (C3) has a non-inverting input (30) coupled to the second input terminal (B), an inverting input (32) coupled to the third junction node (JC), and an output (34) coupled to a third output terminal (BJ). A fourth comparator (C4) has a non-inverting input (40) coupled to the second input terminal (B), an inverting input (42) coupled to the first junction node (JA), and an output (44) coupled to a fourth output terminal (BK). A fifth comparator (C5) has a non-inverting input (50) coupled to the third input terminal (C), an inverting input (52) coupled to the first junction node (JA), and an output (54) coupled to a fifth output terminal (CJ). A sixth comparator (C6) has a non-inverting input (60) coupled to the third input terminal (C), an inverting input (62) coupled to the second junction node (JB), and an output (64) coupled to a sixth output terminal (CK).

Abstract translation: 一种用于三线数字接口的接收机（100），包括耦合在第一输入端（A）和第一结节点（JA）之间的第一电阻元件（R1），耦合在第二电阻元件 输入端子（B）和第二连接节点（JB）以及耦合在第三输入端子（C）和第三连接节点（JC）之间的第三电阻元件（R3）。 包括第一第二和第三网络终端（71,72,73）的网络（70）分别耦合到第一，第二和第三连接节点（JA，JB，JC）。 网络在第一，第二和第三网络终端的所有成对之间具有基本相同的阻抗。 第一比较器（C1）具有耦合到第一输入端子（A）的非反相输入端（10），耦合到第二接点节点（JB）的反相输入端（12）和耦合到第二输入端 第一输出端子（AJ）。 第二比较器（C2）具有耦合到第一输入端（A）的非反相输入（20），耦合到第三结节点（JC）的反相输入端（22）和耦合到第一输入端 第二输出端（AK）。 第三比较器（C3）具有耦合到第二输入端子（B）的非反相输入端（30），耦合到第三接点节点（JC）的反相输入端（32）和耦合到 第三输出端子（BJ）。 第四比较器（C4）具有耦合到第二输入端子（B）的非反相输入端（40），耦合到第一接点节点（JA）的反相输入端（42）和耦合到第一输入端 第四输出端子（BK）。 第五比较器（C5）具有耦合到第三输入端（C）的非反相输入（50），耦合到第一结节点（JA）的反相输入端（52）和耦合到第一输入端 第五输出端（CJ）。 第六比较器（C6）具有耦合到第三输入端（C）的非反相输入端（60），耦合到第二接点节点（JB）的反相输入端（62）和耦合到第二接点 第六输出端（CK）。

公开(公告)号：WO2014195258A1

公开(公告)日：2014-12-11

申请号：PCT/EP2014/061350

申请日：2014-06-02

Applicant: ST-ERICSSON SA

Inventor： SIRITO-OLIVIER, Philippe ,  MILAZZO, Patrizia ,  NAGARI, Angelo

IPC: H03F3/217 ,  H02M3/156 ,  H03K17/693 ,  H02P7/00

CPC classification number: H02M3/158 ,  H03F3/2173 ,  H03F3/2175

Abstract: A circuit comprising: – an output stage according to the invention; – a first control apparatus comprising a control stage of the first control apparatus is connected to the output stage; and, – a second control apparatus comprising a control stage of the second control apparatus is connected to the output stage; wherein, – when the control stage of the first control apparatus is connected to the output stage, the control stage of the second control apparatus is electrically disconnected from the output stage, the output stage being configured to operate in a first operating state; and, – when the control stage of the second control apparatus is connected to the output stage, the control stage of the first control apparatus is electrically disconnected from the output stage, the output stage being configured to operate in a second operating state. The output stage and the use of the output stage are also claimed.

Abstract translation: 一种电路，包括： - 根据本发明的输出级; - 包括第一控制装置的控制级的第一控制装置连接到输出级; 以及 - 包括所述第二控制装置的控制级的第二控制装置连接到所述输出级; 其中，当所述第一控制装置的控制级连接到所述输出级时，所述第二控制装置的控制级与所述输出级电断开，所述输出级被配置为在第一操作状态下操作; 以及 - 当所述第二控制装置的控制级连接到所述输出级时，所述第一控制装置的控制级与所述输出级电断开，所述输出级被配置为在第二操作状态下工作。 输出级和输出级的使用也被要求保护。

公开(公告)号：WO2014173722A1

公开(公告)日：2014-10-30

申请号：PCT/EP2014/057547

申请日：2014-04-14

Applicant: ST-ERICSSON SA

Inventor： RIES, Gilles

IPC: G09G5/393 ,  G09G5/395

CPC classification number: G06T3/60 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  G09G2340/0492

Abstract: A method allows changing an image raster direction from an application raster direction to a screen raster direction, in-flight while pixel values of an image are transferred successively from an application output memory (10) to a display unit (12). A single buffer memory array (11) is implemented between the application output memory and the display unit. Two writing orders for cells of the buffer memory array are used in turn, each combined with a different reading order for said cells. The method can be hardware-implemented, and is adapted for burst-handling of the pixel values.

Abstract translation: 一种方法允许在图像的像素值从应用输出存储器（10）连续地传送到显示单元（12）的同时，将图像光栅方向从应用光栅方向改变到屏幕光栅方向。 在应用输出存储器和显示单元之间实现单个缓冲存储器阵列（11）。 依次使用缓冲存储器阵列的单元的两个写入顺序，每个与用于所述单元的不同读取顺序相结合。 该方法可以是硬件实现的，并且适用于像素值的突发处理。

公开(公告)号：WO2014114632A1

公开(公告)日：2014-07-31

申请号：PCT/EP2014/051111

申请日：2014-01-21

Applicant: ST-ERICSSON SA

Inventor： COONFALONIERI, Pierangelo ,  GUANZIROLI, Federico ,  NICOLLINI, Germano

IPC: H03F3/217 ,  H03F3/30 ,  H03F1/32 ,  H03F1/30

CPC classification number: H03F1/0205 ,  H03F1/307 ,  H03F1/3205 ,  H03F3/183 ,  H03F3/211 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/2173 ,  H03F3/2178 ,  H03F3/3059 ,  H03F3/3064 ,  H03F3/45179 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2203/21142

Abstract: Differential output stage (200) of an amplification device, for driving a load, comprises a first (201) and a second (202) differential output stage portion. The first differential output stage portion (201) comprises: a first (M1PSW) and a second (M1NSW) output circuit; a first driving circuit (210) comprising a first biasing circuit (M2P, M3N, M4N, R11, I11); a second driving circuit (220) comprising a second biasing circuit (I41, R41, M4P, M3P, M2N). The first differential output stage portion (201) comprises: a third output circuit (M2PSW) connected between a first node (N1) of said first biasing circuit (M2P, M3N, M4N, R11, I11 ) and a first differential output terminal (01), having a third driving terminal (DT3) connected to a first driving terminal (DT1); a fourth output circuit (M2NSW) connected between a first node (N4) of the second biasing circuit (I41, R41, M4P, M3P, M2N) and the first differential output terminal (01), having a fourth driving terminal (DT4) connected to a second driving terminal (DT2).

Abstract translation: 用于驱动负载的放大装置的差分输出级（200）包括第一（201）和第二（202）差分输出级部分。 第一差分输出级部分（201）包括：第一（M1PSW）和第二（M1NSW）输出电路; 第一驱动电路（210），包括第一偏置电路（M2P，M3N，M4N，R11，I11）; 包括第二偏置电路（I41，R41，M4P，M3P，M2N）的第二驱动电路（220）。 第一差分输出级部分（201）包括：连接在所述第一偏置电路（M2P，M3N，M4N，R11，I11）的第一节点（N1）和第一差分输出端子（01）之间的第三输出电路（M2PSW） ），具有连接到第一驱动端子（DT1）的第三驱动端子（DT3）; 连接在第二偏置电路（I41，R41，M4P，M3P，M2N）的第一节点（N4）和第一差分输出端子（01）之间的第四输出电路（M2NSW），具有连接的第四驱动端子（DT4） 到第二驱动终端（DT2）。

公开(公告)号：WO2014083008A1

公开(公告)日：2014-06-05

申请号：PCT/EP2013/074764

申请日：2013-11-26

Applicant: ST-ERICSSON SA

Inventor： MICHAL, Vratislav

IPC: H02M3/158

CPC classification number: G01R19/25 ,  H02M3/158 ,  H02M3/1588 ,  Y02B70/1466

Abstract: There is described a circuit and a method of detecting a voltage polarity for the detection of a Continuous Conduction Mode to Discontinuous Conduction Mode boundary of a switched DC-DC converter. There is provided use of a dynamic current mirror to store in a first capacitor (C) a voltage representative of the conduction voltage (V DS(Φ1) )of the power switch, at the end of a conduction cycle of said power switch. Also, an auto-zero comparator is used to charge the output voltage of the dynamic current mirror into a second capacitor (C 2 ), during the first phase of operation corresponding to a conduction cycle of the power switch, and to detect the polarity of the conduction voltage (V DS(t=TCLK ))of the power switch at the end of the first phase of operation of the DC-DC converter, by comparing the voltage stored in the second capacitor during the first phase of operation with the output voltage of the dynamic current mirror in a second phase of operation (Φ 2 ) corresponding to a non-conduction cycle of the power switch.

Abstract translation: 描述了用于检测开关DC-DC转换器的连续导通模式到不连续导通模式边界的电压极性的电路和方法。 在所述电源开关的导通周期结束时，提供使用动态电流镜以在第一电容器（C）中存储表示电源开关的导电电压（VDS（Φ1））的电压。 此外，在对应于电源开关的导通周期的第一操作阶段期间，使用自动归零比较器将动态电流镜的输出电压充电到第二电容器（C2）中，并且检测 在DC-DC转换器的第一工作阶段结束时，通过将在第一操作期间存储在第二电容器中的电压与在第一操作期间的输出电压进行比较，电力开关的导通电压（VDS（t = TCLK）） 在第二阶段的动作电流镜（Φ2）对应于电源开关的非导通周期。

公开(公告)号：WO2014048985A3

公开(公告)日：2014-05-30

申请号：PCT/EP2013069962

申请日：2013-09-25

Applicant: ST ERICSSON SA

Inventor： SUHONEN MARCUS

IPC: H03K5/13 ,  G06F1/04 ,  H03K5/135

CPC classification number: H03K3/012 ,  G05F1/66 ,  G06F1/04 ,  G06F1/3206 ,  H03K5/06 ,  H03K5/133 ,  H03K5/135 ,  H04L7/0037 ,  H04L7/0087 ,  H04L7/0091

Abstract: An integrated circuit (100) comprises a clock generation stage (120) arranged to generate a clock signal having a clock frequency dependent on a reference signal. A delay stage (130) is arranged to generate a delayed clock signal by delaying the clock signal. A control stage (140) is arranged to generate a control signal indicative of a delay of the delayed clock signal relative to the clock signal. A frequency divider (150) arranged to generate a divided signal by dividing a dividend signal having a dividend frequency dependent on the reference signal. A power supply regulator (170) is arranged to supply power to the frequency divider (150) at a first power level, the first power level being dependent on the control signal. power supply controlpower supply control

Abstract translation: 一种集成电路（100）包括时钟生成级（120），其被布置为生成具有取决于参考信号的时钟频率的时钟信号。 延迟级（130）被布置成通过延迟时钟信号来生成延迟时钟信号。 控制级（140）被布置成生成指示延迟的时钟信号相对于时钟信号的延迟的控制信号。 分频器（150），被配置为通过划分具有取决于参考信号的除数频率的除数信号来生成除法信号。 电源调节器（170）被布置成以第一功率电平向分频器（150）供电，第一功率电平取决于控制信号。 电源控制电源控制

公开(公告)号：WO2014076229A1

公开(公告)日：2014-05-22

申请号：PCT/EP2013/073923

申请日：2013-11-15

Applicant: ST-ERICSSON SA

Inventor： PIGNOLO, Philippe

IPC: H02M3/156

CPC classification number: H03K3/017 ,  H02M3/156 ,  H02M2003/1566 ,  H03K3/012

Abstract: A pulse width modulation controller (PWM) is disclosed which has a MOSFET (15) responsive to the error voltage (Verror) signal from the PWM amplifier (17) to detect a transient condition without delay ∆Td. The MOSFET drain generates and applies a detection signal (S) to a delaying circuit (D). The delaying circuit (D) is responsive to the transient detection signal (S) to asynchronously output two latch signals (S1) and (S2) which on application to respective latch circuits (L1, L2) cause a change in conduction state of PMOS (8) and NMOS (9). This arrangement reduces voltage undershoot.

Abstract translation: 公开了一种脉冲宽度调制控制器（PWM），其具有响应于来自PWM放大器（17）的误差电压（Verror）信号的MOSFET（15），以无延迟ΔTd检测瞬态条件。 MOSFET漏极产生并向延迟电路（D）施加检测信号（S）。 延迟电路（D）响应于瞬态检测信号（S）异步地输出两个锁存信号（S1）和（S2），在锁存信号（S1，L2）施加到各个锁存电路（L1，L2）导致PMOS的导通状态 8）和NMOS（9）。 这种布置降低了电压下冲。

公开(公告)号：WO2014072391A1

公开(公告)日：2014-05-15

申请号：PCT/EP2013/073251

申请日：2013-11-07

Applicant: ST-ERICSSON SA

Inventor： CONFALONIERI, Pierangelo ,  GUANZIROLI, Federico ,  MINUTI, Alberto

IPC: H03M1/10 ,  H03M1/46

CPC classification number: H03M1/468 ,  H03M1/1019 ,  H03M1/1023 ,  H03M1/46

Abstract: A new approach is disclosed concerning offset cancellation methods in analog to digital converters and analog to digital converters implementing the same. Such approach allows to efficiently cancel offset drifts in analog to digital converters.

Abstract translation: 公开了一种关于模数转换器和实现相同数字转换器的模数转换器的失调消除方法的新方法。 这种方法允许有效地消除模数转换器中的偏移漂移。

公开(公告)号：WO2014064098A1

公开(公告)日：2014-05-01

申请号：PCT/EP2013/072060

申请日：2013-10-22

Applicant: ST-ERICSSON SA

Inventor： FRELLO, Dario

IPC: H04N7/01 ,  H04N19/142 ,  H04N19/179 ,  H04N19/139 ,  H04N19/44 ,  H04N19/51

CPC classification number: H04N7/014 ,  H04N7/0127 ,  H04N19/139 ,  H04N19/142 ,  H04N19/179 ,  H04N19/44 ,  H04N19/51

Abstract: A method of performing motion compensated frame interpolation on an image sequence comprising coded frames, the method comprising: - decoding the coded frames; - obtaining characteristics of the decoded frames; - determining a group of successive decoded frames that are identical; and, - performing a motion compensated frame interpolation between a first frame and a second frame, the motion compensated frame interpolation being based on at least the characteristics of the group of decoded frames. A computer program product. An apparatus for performing the motion compensated frame interpolation. A wireless device comprising the apparatus.

Abstract translation: 一种在包括编码帧的图像序列上执行运动补偿帧内插的方法，所述方法包括：对编码帧进行解码; - 获得解码帧的特征; - 确定一组相同的连续解码帧; 以及 - 在第一帧和第二帧之间执行运动补偿帧内插，所述运动补偿帧内插至少基于所述解码帧组的特征。 电脑程式产品 一种用于执行运动补偿帧内插的装置。 一种包括该装置的无线装置。

公开(公告)号：WO2014060459A1

公开(公告)日：2014-04-24

申请号：PCT/EP2013/071600

申请日：2013-10-16

Applicant: ST-ERICSSON SA

Inventor： THORELL, Per ,  GULLBERG, Mikael ,  MÖHLE, Marco

IPC: H04M1/725 ,  H04W8/22

CPC classification number: H04W8/24

Abstract: A wireless modem for configuration of one or more features for the wireless modem is provided. The wireless modem comprises a database comprising multiple layers. Each layer out of the multiple layers is related to a level of priority. The method comprises configuring the content of the layers in the database by loading at least one parameter value into a specific layer out of the multiple layers. The method further comprises requesting a specific parameter in the database, which specific parameter out of a set of parameters is present in more than one of the multiple layers and returning from the database a value for the specific parameter from a layer with the highest level of priority out of the multiple layers. According to other aspects, other embodiments herein relate to a wireless modem, a wireless device and to an integrated circuit.

Abstract translation: 提供了一种用于配置无线调制解调器的一个或多个特征的无线调制解调器。 无线调制解调器包括包括多个层的数据库。 多层中的每个层与优先级相关。 该方法包括通过将至少一个参数值加载到多个层中的特定层中来配置数据库中的层的内容。 该方法还包括请求数据库中的特定参数，一组参数中的哪个特定参数存在于多个层中的多于一个层中，并从数据库返回具有最高级别的层的特定参数的值 优先考虑多层次。 根据其他方面，本文的其它实施例涉及无线调制解调器，无线设备和集成电路。