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公开(公告)号：WO2019091358A1
公开(公告)日：2019-05-16
申请号：PCT/CN2018/114041
申请日：2018-11-06
Applicant: 深圳锐越微技术有限公司
IPC: H03M1/12
CPC classification number: H03M1/1245 , H03M1/468
Abstract: 本申请公开一种N位混合结构模数转换器及包括其的集成电路芯片，该模数转换器器包括前级采样电容阵列、后级电容阵列以及比较器组，前级采样电容阵列包括2N-1组并列排布的第一电容阵列单元，第一电容阵列单元包括两组并联电容串，并联电容串的输入端分别与差分模拟信号及第一预设参考信号切换连接，输出端分别与比较器组的输入端连接，后级电容阵列的输入端分别与比较器组的输出及差分模拟信号切换连接，后级电容阵列的输出端作为模数转换器的输出；该N位混合结构模数转换器的纯电容阵列对于模拟差分信号友好；模拟差分信号的两路差分输入可共用同一比较器单元。
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2.发明申请STATISTICAL ESTIMATION-BASED NOISE REDUCTION TECHNIQUE FOR LOW POWER SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTERS 审中-公开用于低功率随机逼近的基于统计估计的噪声减少技术寄存器模拟到数字转换器
公开(公告)号：WO2017058874A1
公开(公告)日：2017-04-06
申请号：PCT/US2016/054117
申请日：2016-09-28
Inventor： SUN, Nan , CHEN, Long , TANG, Xiyuan
CPC classification number: H03M1/08 , H03M1/04 , H03M1/0697 , H03M1/1009 , H03M1/38 , H03M1/468
Abstract: Disclosed herein are systems and methods that describe statistical estimation based noise reduction for SAR ADCs. For SAR ADCs, the conversion error can be available at the comparator input. Although a noisy 1-bit comparator may not be able to produce an accurate estimation for its input if used only once, the comparison can be repeated multiple times for a designated bit of the multi-bit SAR ADC. This can allow for the improvement of the estimation accuracy by examining the probability of the comparator output being "1" or "0". The estimation of a signal from a noisy environment using multiple trials can be cast as a classic. In one aspect of the disclosure, an optimal Bayes estimator is disclosed to achieve a low estimation error from the comparator on a designated bit of the multi-bit SAR ADC.
Abstract translation: 这里公开了描述针对SAR ADC的基于噪声降低的统计估计的系统和方法。 对于SAR ADC，转换错误可在比较器输入端使用。 尽管如果只使用一次，噪声1比特比较器可能无法产生其输入的精确估计，所以可以对多位SAR ADC的指定位重复多次比较。 这可以通过检查比较器输出的概率为“1”或“0”来提高估计精度。 使用多次试验的嘈杂环境中的信号估计可以作为经典。 在本公开的一个方面，公开了一种最佳贝叶斯估计器，以在多位SAR ADC的指定位上从比较器获得低估计误差。
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公开(公告)号：WO2016106478A1
公开(公告)日：2016-07-07
申请号：PCT/CN2014/095254
申请日：2014-12-29
Applicant: 中国科学院半导体研究所
CPC classification number: H04N5/378 , H03M1/02 , H03M1/1047 , H03M1/468 , H03M1/804
Abstract: 一种用于CMOS图像传感器的模拟读出预处理电路及其控制方法。该模拟读出预处理电路包括：扩展计数型积分循环-逐次逼近混合型模数转换电容网络（1），用于实现CMOS图像传感器输出信号的读出和模数转换；运算放大器（2），用于利用运算放大器两输入端"虚短"及电荷守恒原理，实现扩展计数型积分循环-逐次逼近混合型模数转换的功能，扩展计数型积分可有效降低图像传感器内部的热噪声和闪烁噪声；比较器（3），用于比较两端电压的大小，完成信号量化功能；以及控制信号发生器（4），用于提供控制信号。
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公开(公告)号：WO2016087869A1
公开(公告)日：2016-06-09
申请号：PCT/GB2015/053708
申请日：2015-12-03
Applicant: ATLANTIC INERTIAL SYSTEMS LIMITED
Inventor： DURSTON, Michael Terrence , TOWNSEND, Kevin , SITCH, Douglas Robert
Abstract: A successive approximation Analogue to Digital Converter (ADC), comprising: a sample and hold device arranged to sample and hold an input signal at the beginning of a conversion cycle; a successive approximation register that sequentially builds up a digital output from its most significant bit to its least significant bit; a digital to analogue converter that outputs a signal based on the output of the successive approximation register; a comparator that compares the output of the digital to analogue converter with an output of the sample and hold device and supplies its output to the successive approximation register; and a residual signal storage device arranged to store the residual signal at the end of a conversion cycle; and wherein the successive approximation ADC is arranged to add the stored residual signal from the residual signal storage device to the input signal stored on the sample and hold device at the start of each conversion cycle. After each ADC full conversion by the SAR, the analogue conversion of the digital output is as close to the original input signal as the resolution will allow. However there remains the residual part of the input signal that is smaller than what can be represented by the least significant bit of the digital output of the SAR. In normal operation, successive outputs of a SAR for the same input will result in the same digital value output and the same residual. By storing the residual at the end of each conversion and adding the residual onto the input signal of the next conversion the residuals are accumulated over time so that they may affect the output digital value. After a number of conversions, the accumulated residuals add up to more than the value represented by the LSB of the register and the digital value will be one higher than if a conversion had been performed on the input signal alone. In this way, the residual signal affects the output value in time and thus can be taken into account by processing the digital output in the time domain.
Abstract translation: 一种逐次逼近的模数转换器（ADC），包括：采样和保持装置，被布置成在转换周期开始时对输入信号进行采样和保持; 逐次逼近寄存器，从最高有效位到其最低有效位顺序建立数字输出; 数模转换器，其基于逐次逼近寄存器的输出输出信号; 比较器，将数模转换器的输出与采样和保持装置的输出进行比较，并将其输出提供给逐次逼近寄存器; 以及残余信号存储装置，被布置成在转换周期结束时存储所述残余信号; 并且其中所述逐次逼近ADC被布置为在每个转换周期开始时将存储的残留信号从残留信号存储装置添加到存储在采样和保持装置上的输入信号。 在通过SAR进行每次ADC完全转换后，数字输出的模拟转换与分辨率允许的原始输入信号相近。 然而，输入信号的剩余部分仍然比由SAR的数字输出的最低有效位表示的少。 在正常操作中，相同输入的SAR的连续输出将导致相同的数字值输出和相同的残差。 通过在每个转换结束时存储残差，并将残差加到下一转换的输入信号上，残差随着时间的推移而累积，从而可能影响输出数字值。 经过多次转换后，累计残差加起来高于寄存器LSB的值，数字值比单独输入信号进行转换时要高一个。 以这种方式，残留信号及时影响输出值，因此可以通过在时域中处理数字输出来考虑。
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5.发明申请LOW POWER HIGH RESOLUTION ANALOGUE TO DIGITAL CONVERTER AND METHOD THEREOF 审中-公开低功率高分辨率数字转换器的模拟及其方法
公开(公告)号：WO2013015672A1
公开(公告)日：2013-01-31
申请号：PCT/MY2012/000143
申请日：2012-06-22
Applicant: MIMOS BERHAD , TAN, Kong Yew
Inventor： TAN, Kong Yew
IPC: H03M1/14
Abstract: The present invention provides a hybrid analogue-to-digital converter (ADC) that comprises a successive approximation analogue-to-digital converter (SAR-ADC); and a time based integrating and cyclic analogue-to-digital converter (CYC-ADC) integrated with the SAR-ADC. An input analogue signal is processed through the SAR-ADC to output a first output constituting most significant bits (MSBs) of an digital output signal and a residue signal, the residue signal is further processed through the CYC-ADC to output a second output constituting the least significant bits (LSBs). A method of carrying out the analogue to digital conversion is also provided.
Abstract translation: 本发明提供一种包括逐次逼近模数转换器（SAR-ADC）的混合模拟 - 数字转换器（ADC）; 以及与SAR-ADC集成的基于时间的积分和循环模数转换器（CYC-ADC）。 通过SAR-ADC处理输入模拟信号，以输出构成数字输出信号和残留信号的最高有效位（MSB）的第一输出，残留信号通过CYC-ADC进一步处理，以输出构成 最低有效位（LSB）。 还提供了一种执行模数转换的方法。
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Patent Agency Ranking
公开(公告)号：WO2012151491A3
公开(公告)日：2013-01-31
申请号：PCT/US2012036529
申请日：2012-05-04
Applicant: TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN , WANG YAN , KALTHOFF TIMOTHY V , WU MICHAEL A
Inventor： WANG YAN , KALTHOFF TIMOTHY V , WU MICHAEL A
CPC classification number: H03M1/1295 , H03M1/468
Abstract: A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN + ) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN -) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage. The bottom plate of the first capacitor is coupled to a second reference voltage (VDD or VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.
Abstract translation: 开关电容电路（10,32或32A）通过将求和导体（13）的顶板切换到第一参考电压（VSS）将第一信号（VIN +）取样到第一电容器（C1或CIN1）上， 并将其底板切换到第一信号。 将第二信号（VIN-）通过将其顶板切换到第二信号并将其底板切换到第一参考电压而被采样到第二电容器（C3或CIN3）上。 在采样之后，第二电容器的顶板耦合到第一电容器的顶板。 第二电容器的底板耦合到第一参考电压。 第一电容器的底板耦合到第二参考电压（VDD或VREF），从而从第一导体（13）消除共模输入电压分量的至少一部分，将采样的差分电荷保持在求和 并在其上建立预定的共模电压，并且防止求和导体具有允许从其中泄漏电荷的电压。 开关电容电路可以是SAR，积分器或放大器。
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公开(公告)号：WO2010039330A1
公开(公告)日：2010-04-08
申请号：PCT/US2009/052822
申请日：2009-08-05
Applicant: FREESCALE SEMICONDUCTOR INC. , FEDDELER, James, R. , BERENS, Michael, T.
Inventor： FEDDELER, James, R. , BERENS, Michael, T.
CPC classification number: H03M1/1038 , H03M1/1071 , H03M1/468 , H03M1/68 , H03M1/804
Abstract: A data converter (12) for converting analog signals to digital signals, or for converting digital signals to analog signal is provided. In one embodiment, a production self-test (520 of FIG. 19; 570 of FIG. 20) is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided (620 of FIG. 22). In one embodiment, a data converter with a more stable comparator common mode voltage is provided (320 of FIG. 15). In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration (see 271 of FIG. 11). In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided (150 of FIG. 5; 170 of FIG. 6).
Abstract translation: 提供一种用于将模拟信号转换为数字信号或将数字信号转换为模拟信号的数据转换器（12）。 在一个实施例中，提供了生产自检（图19的520;图20的570）。 在一个实施例中，提供了用于数据转换器的高速低分辨率方法或模式（图22的620）。 在一个实施例中，提供具有更稳定的比较器共模电压的数据转换器（图15的320）。 在一个实施例中，提供和维护数字校准的数据转换器的输入范围，使得由于校准而不存在输入范围的损失（参见图11的271）。 在一个实施例中，提供了使用先前存储的校准值的未校准结果的数字后处理（图5的150;图6的170）。
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公开(公告)号：WO2008146302A3
公开(公告)日：2009-10-15
申请号：PCT/IN2008000159
申请日：2008-03-17
Applicant: ANALOG DEVICES INC , NITTALA SRIKANTH , GORBOLD JEREMY , MADHAVAN MAHESH
Inventor： NITTALA SRIKANTH , GORBOLD JEREMY , MADHAVAN MAHESH
IPC: H03M1/38
CPC classification number: H03M1/462 , H03M1/0673 , H03M1/468 , H03M1/687
Abstract: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.
Abstract translation: 公开了用于使用并行数字数据路径将模拟值转换成数字等效的用于转换器（ADC）的模拟数字转换器。 在一个示例实施例中，ADC包括具有经由模拟采样和保持电路接收模拟值的输入的开关电容器DAC。 比较器耦合到开关电容器DAC。 逐次逼近寄存器（SAR）耦合到比较器。 多个逻辑块耦合到SAR。 多个温度测量编码器耦合到相关联的多个逻辑块。 多个MUX耦合到相关联的多个温度测量编码器和比较器，其中多个MUX具有耦合到开关电容器DAC的输入的相关输出。
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公开(公告)号：WO2009010581A1
公开(公告)日：2009-01-22
申请号：PCT/EP2008/059446
申请日：2008-07-18
Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBH , OHNHAEUSER, Frank , WICKMANN, Andreas
Inventor： OHNHAEUSER, Frank , WICKMANN, Andreas
CPC classification number: H03M1/129 , H03M1/0682 , H03M1/468
Abstract: A method for analog-to-digital conversion is provided using successive approximation and a plurality of capacitors comprising a first set of capacitors and a second set of capacitors, a first side of each of the plurality of capacitors being coupled to a common node. The method comprises sampling an input voltage on the first set of capacitors, after the step of sampling leaving a side of at least one capacitor of the first set of capacitors floating, coupling a capacitor of the first set of capacitors, which is not floating, with a capacitor of the second set of capacitors so as to redistribute the charge on the coupled capacitors, comparing the voltage on the common node with a comparator reference voltage level to receive a comparison result to be used for a bit decision, and switching the floating side of the floating capacitor of the first set of capacitors to either a first reference voltage or a second reference voltage in accordance with the bit decision.
Abstract translation: 使用逐次近似来提供用于模数转换的方法，以及包括第一组电容器和第二组电容器的多个电容器，多个电容器中的每一个的第一侧耦合到公共节点。 该方法包括在采样步骤之后对第一组电容器上的输入电压进行采样，使第一组电容器的至少一个电容器的一侧浮动，耦合不浮置的第一组电容器的电容器， 利用第二组电容器的电容器来重新分配耦合电容器上的电荷，将公共节点上的电压与比较器参考电压电平进行比较，以接收用于比特决策的比较结果，并且切换浮动 根据比特决定将第一组电容器的浮动电容器的侧面设置为第一参考电压或第二参考电压。
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公开(公告)号：WO2008008271A2
公开(公告)日：2008-01-17
申请号：PCT/US2007015524
申请日：2007-07-06
Applicant: ANALOG DEVICES INC , HURRELL CHRISTOPHER PETER
Inventor： HURRELL CHRISTOPHER PETER
IPC: H03M1/46
CPC classification number: H03M1/002 , H03K17/04123 , H03K17/162 , H03K17/6872 , H03K19/0013 , H03M1/0863 , H03M1/462 , H03M1/466 , H03M1/468 , H03M1/804
Abstract: A successive approximation analog to digital converter comprising a plurality of capacitors which during a successive approximation conversion are selectively connectable to a first reference or a second reference under the command of a controller, wherein during a conversion step where the connections of a given capacitor may be varied the switches to the given capacitor are both placed in a high impedance state during a decision period of a comparator.
Abstract translation: 包括多个电容器的逐次逼近模数转换器，其在逐次逼近转换期间可在控制器的命令下选择性地连接到第一参考或第二参考，其中在转换步骤期间，给定电容器的连接可以是 在比较器的判定周期期间将开关变化到给定电容器都被置于高阻抗状态。
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