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公开(公告)号：WO2006040706A3
公开(公告)日：2006-08-24
申请号：PCT/IB2005053229
申请日：2005-09-30
Applicant: KONINKL PHILIPS ELECTRONICS NV , SANDULEANU MIHAI A T , STIKVOORT EDUARD F
Inventor： SANDULEANU MIHAI A T , STIKVOORT EDUARD F
IPC: H03K19/003
CPC classification number: H03F1/02 , H03F3/217 , H03F3/30 , H03F3/45089 , H03F2203/45248 , H03F2203/45366 , H03K17/16
Abstract: The present invention provides a driving circuit (100) in particular for driving a laser diode (700) or a modulator, at data speed in the order of Gb/s. The driving circuit (10) has a low-voltage, high-speed output stage capable of driving efficiently a laser diode (700) or a modulator. The driver circuit (10) comprises a chain of circuits, said chain comprising a slew-rate control circuit, at least one translinear amplifier (200, 201, 202), a push/pull stage (300), and an output stage (400) for driving the load current. Due to its versatility, the driver can be used in other applications e.g. line drivers, cable drivers, high-speed serial interfaces for back-plane interconnect, etc. The driver can work at low supply voltages, e.g. 3.3V nominal down to 2.7V, with high power efficiency. One major clue is to use entirely the large signal current produced by the output stage, e.g. in the driven laser diode, without wasting current in supply lines.
Abstract translation: 本发明提供一种驱动电路（100），特别是以Gb / s的数量速度驱动激光二极管（700）或调制器。 驱动电路（10）具有能够有效驱动激光二极管（700）或调制器的低电压，高速输出级。 所述驱动电路（10）包括电路链，所述链包括压摆率控制电路，至少一个跨导放大器（200,201,202），推/拉级（300）和输出级（400） ）用于驱动负载电流。 由于其多功能性，驾驶员可以用于其他应用，例如 线路驱动器，电缆驱动器，用于背板互连的高速串行接口等。驱动器可以在低电源电压下工作，例如， 3.3V标称低至2.7V，具有高功率效率。 一个主要线索是完全使用由输出级产生的大信号电流，例如， 在驱动激光二极管中，不会浪费供电线路中的电流。
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公开(公告)号：WO2005041413A1
公开(公告)日：2005-05-06
申请号：PCT/IB2004/052080
申请日：2004-10-13
Inventor： STIKVOORT, Eduard, F. , SANDULEANU, Mihai, A., T.
IPC: H03K23/54
CPC classification number: H03K23/44 , H03K23/542
Abstract: A frequency divider comprising a first flip-flop (M1, M2, M3, M4) having a first clock input (CI) for receiving a clock signal, the flip-flop further comprising a first set input (Q4) and a first non-inverted output (Q1). The frequency divider further comprises a second flip-flop (M'1, M'2, M'3, M'4) having a second clock input (Cl) for receiving a second clock signal that is substantially in anti-phase with the clock signal inputted into the first clock input (Cl), a second set input coupled to the first non-inverted output (Q1), a second non-inverted output (Q2) and a second inverted output (Q2), the second inverted output (Q2) being coupled to the first set input (Q4).
Abstract translation: 一种分频器，包括具有用于接收时钟信号的第一时钟输入（CI）的第一触发器（M1，M2，M3，M4），所述触发器还包括第一设定输入（Q4）和第一非 - 反相输出（Q1）。 分频器还包括具有第二时钟输入（C1）的第二触发器（M'1，M'2，M'3，M'4），用于接收与第二时钟信号基本上相反的第二时钟信号 输入到第一时钟输入（C1）的时钟信号，耦合到第一非反相输出（Q1）的第二设定输入，第二非反相输出（Q2）和第二反相输出（Q2），第二反相输出 （Q2）耦合到第一组输入（Q4）。
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公开(公告)号：WO2005041412A1
公开(公告)日：2005-05-06
申请号：PCT/IB2004/052079
申请日：2004-10-13
Inventor： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
IPC: H03K23/54
CPC classification number: H03K23/44 , H03K23/542
Abstract: A prescaler, comprising a first flip-flop (F1) coupled to a second flip-flip (F2). Each flip-flop comprises a latch (M1, M2, M3, M4) having a first input (R) and a second input (S) coupled to respective first NOR circuit (M8, M9, M10) and second NOR circuit (M5, M6, M7).
Abstract translation: 一种预分频器，包括耦合到第二触发器（F2）的第一触发器（F1）。 每个触发器包括具有耦合到相应的第一NOR电路（M8，M9，M10）和第二NOR电路（M5）的第一输入（R）和第二输入（S）的锁存器（M1，M2，M3，M4） M6，M7）。
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公开(公告)号：WO2007057804A1
公开(公告)日：2007-05-24
申请号：PCT/IB2006/054040
申请日：2006-11-01
Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , ADITHAM, Ram, P. , STIKVOORT, Eduard, F.
Inventor： SANDULEANU, Mihai, A., T. , ADITHAM, Ram, P. , STIKVOORT, Eduard, F.
IPC: H03C5/00
CPC classification number: H03C5/00
Abstract: The present invention relates to a polar modulation apparatus and method, in which a polar-modulated signal is generated based on separately processed phase modulation (PM) and amplitude modulation (AM) components of an input signal. An amplified polar modulated output signal is generated in accordance with the phase modulation and amplitude modulation components by using a differential power amplifier circuitry(30) and supplying an amplified phase modulation component to a differential input of the differential power amplifier circuitry(30). A bias input of the differential power amplifier circuitry(30) is controlled based on the amplitude modulation component, so as to modulate a common-mode current of the differential power amplifier circuitry(30). Thereby, a new concept of a polar modulator with static DC-DC converter and power and/or efficiency and/or linearity controlled output power amplifier can be achieved.
Abstract translation: 本发明涉及极化调制装置和方法，其中基于输入信号的分别处理的相位调制（PM）和调幅（AM）分量产生极调调制信号。 通过使用差分功率放大器电路（30）根据相位调制和幅度调制分量产生放大的极化调制输出信号，并将放大的相位调制分量提供给差分功率放大器电路（30）的差分输入。 基于幅度调制分量来控制差分功率放大器电路（30）的偏置输入，以便调制差分功率放大器电路（30）的共模电流。 因此，可以实现具有静态DC-DC转换器和功率和/或效率和/或线性控制的输出功率放大器的极性调制器的新概念。
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公开(公告)号：WO2006109214A1
公开(公告)日：2006-10-19
申请号：PCT/IB2006/051033
申请日：2006-04-04
Inventor： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F.
CPC classification number: H03F3/3432 , H03F1/34 , H03F3/195 , H03F3/347 , H03F2200/09 , H03F2200/144 , H03F2200/294 , H03F2200/36 , H03F2200/372
Abstract: A broadband amplifier (2) for receiving radio frequency signals from an antenna (4) is disclosed. The amplifier comprises a first amplifier stage (6) for receiving an input voltage signal, and a first feedback stage (12) for providing a feedback link between an input and an output of the first amplifier stage (6). A second amplifier stage (10) is connected to an output of the first amplifier stage (6) and a second feedback stage (16) provides a feedback link from an output of the second amplifier stage to an input of the first amplifier stage. An output voltage signal is provided at an output terminal (22) of an output stage (20).
Abstract translation: 公开了一种用于从天线（4）接收射频信号的宽带放大器（2）。 放大器包括用于接收输入电压信号的第一放大级（6）和用于在第一放大级（6）的输入和输出之间提供反馈链路的第一反馈级（12）。 第二放大器级（10）连接到第一放大器级（6）的输出，第二反馈级（16）提供从第二放大器级的输出到第一放大级的输入的反馈链路。 在输出级（20）的输出端（22）处提供输出电压信号。
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Patent Agency Ranking
公开(公告)号：WO2006079966A3
公开(公告)日：2006-10-12
申请号：PCT/IB2006050242
申请日：2006-01-23
Applicant: KONINKL PHILIPS ELECTRONICS NV , SANDULEANU MIHAI A T , STIKVOORT EDUARD F , TOMBEUR ANTOON M H
Inventor： SANDULEANU MIHAI A T , STIKVOORT EDUARD F , TOMBEUR ANTOON M H
IPC: H03K3/2885
CPC classification number: H03K3/2885
Abstract: Devices (101-105) comprising latches (1-3) with tracking circuits (4) for, in tracking modes, tracking data signals and with deciding circuits (5) for, in deciding modes, deciding about the data signal can use their available time more efficiently by, in the tracking modes, preparing the deciding circuits (5). Thereto, the deciding circuits (5) are not to be switched between disabled/enabled situations, but are to be kept enabled. The tracking circuits (4), in the tracking modes, supply signal values derived from the data signals to the deciding circuits (5), and the deciding circuits (5), in the deciding modes, amplify the signal values. The tracking circuits (4) comprise diodes (21,22) to allow reduced voltage swings in the data signals to be sufficient for proper performances of the latch (1-3). Such reduced voltage swings allow the latches (1-3) to perform at higher speeds. The parasitic capacitors present between the cathodes of the diodes (21,22) form capacitances for storing the signal values and allow the deciding circuits (5) to be prepared.
Abstract translation: 包括具有跟踪电路（4）的锁存器（1-3）的设备（101）用于在跟踪模式中跟踪数据信号并且与决定电路（5）用于在决定模式时决定数据信号可以使用它们的可用 通过在跟踪模式中准备决定电路（5）更有效。 此外，决定电路（5）不在禁用/启用情况之间切换，而是保持启用状态。 跟踪电路（4）在跟踪模式中将来自数据信号的信号值提供给决定电路（5），决定电路（5）在决定模式中放大信号值。 跟踪电路（4）包括二极管（21,22），以允许数据信号中的电压摆动减小足以使锁存器（1-3）的适当性能。 这种减小的电压摆动允许锁存器（1-3）以更高的速度执行。 存在于二极管（21,22）的阴极之间的寄生电容器形成用于存储信号值的电容并允许准备确定电路（5）。
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公开(公告)号：WO2005076478A1
公开(公告)日：2005-08-18
申请号：PCT/IB2005/050286
申请日：2005-01-25
Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F. , CISSÉ, Idrissa
Inventor： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F. , CISSÉ, Idrissa
IPC: H03K19/086
CPC classification number: H03K3/356043
Abstract: A latch circuit (1) comprising, a differential input with an inverting input (D+) and a non-inverting input (D-). The latch further comprises a differential output with an inverting output (Q+) and a non-inverting output (Q-). One of the outputs (Q-) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (V cM ) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output s in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold, respectively.
Abstract translation: 一种锁存电路（1），包括具有反相输入（D +）和非反相输入（D-）的差分输入。 锁存器还包括具有反相输出（Q +）和非反相输出（Q-）的差分输出。 输出（Q-）中的一个耦合到具有相反极性的输入（D +）之一。 锁存器还包括控制输入，用于接收用于确定输入信号（In）的阈值的控制信号（VcM），使得如果输入信号大于阈值，则非反相输出s处于HIGH逻辑状态，以及 如果输入信号分别小于阈值，则处于LOW状态。
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公开(公告)号：WO2004093355A1
公开(公告)日：2004-10-28
申请号：PCT/IB2004/050413
申请日：2004-04-08
Inventor： VAUCHER, Cicero, S. , STIKVOORT, Eduard, F.
IPC: H04B17/00
CPC classification number: H04B1/28 , H03J1/0008 , H03J2200/29 , H03L7/16
Abstract: A calibrating system for a receiver receiving an input signal (Rf) having an input frequency (fRf) and working in a receiving mode (R) and in a calibrating mode (C) comprising an intermediate frequency circuit (IF) coupled to a first mixer and comprising a bulk acoustic wave filter (BAW) determining the intermediate frequency (BAWf). The calibrating system further comprises a level detecting circuit (LD) coupled to the intermediate frequency circuit (IF) via a first switch (S1) in the calibrating mode (C) for determining an amplitude of the intermediate frequency signal. The receiver includes a tuning control processor (TC) coupled to the first synthesizer (LO1) and to the second synthesizer (L02) controlling the frequencies generated by said synthesizers (LO1, L02). A level detecting circuit (LD) is coupled to the intermediate frequency circuit (IF) for determining an amplitude of the intermediate frequency signal and providing a signal indicative for said amplitude to the tuning control processor (TC). The system further comprises a register (Reg) coupled to the tuning control processor (TC) for memorizing a number corresponding to the intermediate frequency (BAWf), the number being used as a correction factor for the first and second synthesizers (LO I, L02) in the receiving mode (R).
Abstract translation: 一种用于接收接收具有输入频率（fRf）并且以接收模式（R）工作的校准模式（C））的输入信号（Rf）的接收机的校准系统，包括耦合到第一混频器的中频电路（IF） 并且包括确定中间频率（BAWf）的体声波滤波器（BAW）。 校准系统还包括经由校准模式（C）中的第一开关（S1）耦合到中频电路（IF）的电平检测电路（LD），用于确定中频信号的幅度。 接收机包括耦合到第一合成器（LO1）的调谐控制处理器（TC）和控制由所述合成器（LO1，L02）产生的频率的第二合成器（L02）。 电平检测电路（LD）耦合到中频电路（IF），用于确定中频信号的幅度，并向调谐控制处理器（TC）提供指示所述振幅的信号。 该系统还包括耦合到调谐控制处理器（TC）的寄存器（Reg），用于存储对应于中间频率（BAWf）的数字，该数字被用作第一和第二合成器（LO I，L02 ）在接收模式（R）中。
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公开(公告)号：WO2007148282A2
公开(公告)日：2007-12-27
申请号：PCT/IB2007/052343
申请日：2007-06-19
Inventor： STIKVOORT, Eduard, F. , SANDULEANU, Mihai, A. T.
CPC classification number: H03B5/1231 , H03B5/1215 , H03B5/1218 , H03B5/1221 , H03B5/1271 , H03B2200/0058 , H03B2201/0208 , H03H11/481
Abstract: The invention relates to an electronic device for controlling a controlled oscillator. The electronic device provides a control input for supplying a control signal for tuning the oscillating frequency of the oscillator. Further the electronic device provides a transconductor having a transfer function in the frequency range with a substantially first- order high frequency roll off characteristic. The transconductor is adapted to be coupled to a tank circuit (L0, C0) and to act as a variable capacitance, such that the control signal controls the value of the variable capacitance of the transconductor for tuning the oscillating frequency of the controlled oscillator.
Abstract translation: 本发明涉及一种用于控制受控振荡器的电子设备。 电子装置提供用于提供用于调谐振荡器的振荡频率的控制信号的控制输入。 此外，电子设备提供具有基本上一级高频滚降特性的频率范围内的传递函数的跨导体。 跨导体适于耦合到储能电路（L0，C0）并用作可变电容，使得控制信号控制用于调谐受控振荡器的振荡频率的跨导体的可变电容的值。
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公开(公告)号：WO2007036849A1
公开(公告)日：2007-04-05
申请号：PCT/IB2006/053403
申请日：2006-09-20
Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F. , IONITA, Razvan-Adrian
CPC classification number: H03B27/00 , H03B5/1212 , H03B5/1218 , H03B5/1228 , H03B5/1265 , H03B5/1271 , H03B2200/0074
Abstract: The present invention relates to a differential oscillator circuit and a method of controlling the frequency of an oscillator signal. An enhanced frequency tuning mechanism is provided for controlling the frequency of the oscillator signal. The frequency tuning mechanism comprises first frequency control circuitry for controlling the threshold voltage of respective load transistors (M3, M4) of the differential oscillator circuit, and second frequency control circuitry for controlling at least one of a common-mode current (I BIAS ) flowing through branches of said differential oscillator circuit, a tail current (I TUNE ) of an additional feedback circuit (M5, M6) cross-coupled between the drains of a differential transistor stage (Ml, M2) of said differential oscillator and respective gates of said load transistors (M3, M4), and a voltage applied at a middle point of a tapped coil of a resonating circuit of the differential oscillator circuit. Thereby, a linear fine tuning characteristic can be obtained, where the tuning mechanism may for example work as a "gear-box" by stepping coarsely with the first frequency control circuitry through fine intervals generated by the second frequency control circuitry.
Abstract translation: 本发明涉及一种差分振荡器电路和一种控制振荡器信号的频率的方法。 提供了一种用于控制振荡器信号的频率的增强型频率调谐机构。 频率调谐机构包括用于控制差分振荡器电路的各个负载晶体管（M3，M4）的阈值电压的第一频率控制电路，以及用于控制共模电流（I SUB）中的至少一个的第二频率控制电路， BIAS）流过所述差分振荡器电路的分支，在差动晶体管级的漏极之间交叉耦合的附加反馈电路（M5，M6）的尾电流（IOUT TUNE＆lt; / SUB） （M1，M2）和所述负载晶体管（M3，M4）的各个栅极以及施加在差分振荡器电路的谐振电路的抽头线圈的中点处的电压。 由此，可以获得线性微调特性，其中调谐机构可以例如通过与第一频率控制电路粗略地步进通过由第二频率控制电路产生的精细间隔而作为“变速箱”工作。
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