-
公开(公告)号：WO2006075307A2
公开(公告)日：2006-07-20
申请号：PCT/IB2006050122
申请日：2006-01-13
Applicant: KONINKL PHILIPS ELECTRONICS NV , DARRIET STEPHANE , VAUCHER CICERO S
Inventor： DARRIET STEPHANE , VAUCHER CICERO S
Abstract: The present invention relates to a switching arrangement and method of manufacturing such an arrangement, wherein first and second series-shunt diode structures (D1/D2, D3/D4) are connected to each other in a mirrored configuration to obtain a basic switching cell. This basic switching cell can be used to build a SPDT switch which in turn can be used to build a DPDT switch or switches of higher complexity. Thereby, high isolation and low power consumption can be achieved with the additional advantage of modularity.
Abstract translation: 本发明涉及一种制造这种结构的开关装置和方法，其中第一和第二串联分流二极管结构（D1 / D2，D3 / D4）以镜像配置相互连接以获得基本的开关单元。 该基本开关单元可用于构建SPDT开关，该开关又可用于构建更复杂的DPDT开关或开关。 因此，可以通过模块化的额外优点实现高隔离度和低功耗。
-
公开(公告)号：WO2003065586A3
公开(公告)日：2003-08-07
申请号：PCT/IB2003/000130
申请日：2003-01-20
Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. , NAUTA, Bram , VAN DE BEEK, Remco, C., H. , VAUCHER, Cicero, S.
Inventor： NAUTA, Bram , VAN DE BEEK, Remco, C., H. , VAUCHER, Cicero, S.
IPC: H03L7/197
Abstract: The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.
-
公开(公告)号：WO03065586A2
公开(公告)日：2003-08-07
申请号：PCT/IB0300130
申请日：2003-01-20
Applicant: KONINKL PHILIPS ELECTRONICS NV , NAUTA BRAM , VAN DE BEEK REMCO C H , VAUCHER CICERO S
Inventor： NAUTA BRAM , VAN DE BEEK REMCO C H , VAUCHER CICERO S
CPC classification number: H03L7/095 , H03L7/0891 , H03L7/107 , H03L7/197
Abstract: The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.
Abstract translation: 锁相环（PLL）电路及其控制方法技术领域本发明涉及锁相环（PLL）电路和控制这种PLL电路的方法，其中输入参考信号的频率和从输出振荡信号导出的反馈信号的频率除以 从而降低PLL电路的相位检测装置（1）的频率。 响应于PLL电路的锁相状态的检测，禁止分频步骤。 因此，在实现了相位锁定之后，从循环中除去添加了减小比较频率的额外的参考分频器（6），从而能够增加环路带宽并减小环路内的分频比。
-
公开(公告)号：WO2005093954A1
公开(公告)日：2005-10-06
申请号：PCT/IB2005/050925
申请日：2005-03-16
Inventor： VAUCHER, Cicero, S. , APOSTOLIDOU, Melania
IPC: H03L7/00
CPC classification number: H03L7/00
Abstract: Frequency dividers (2) comprising a first transistor circuit (21) with four transistor pairs (31-34, 81-84), two gate pairs (31, 33, 81, 83) and two latch pairs (32, 34, 82, 84) and comprising a second transistor circuit (22) with two transistor pairs (35-36, 85-86) and comprising an impedance circuit (23) have a relatively low frequency reach. By replacing the prior art load resistors in the impedance circuit (23) by active load impedances comprising transistors (37-40, 87-90), the frequency reach of the frequency divider (2) is improved significantly. An impedance (41-44) coupled to the emitter of a transistor (37-40, 87-90) defines the operation frequency range of the frequency divider (2), and an impedance (45-48) coupled to the basis of a transistor (37-40, 87-90) allows the frequency divider (2) to be tuned for maximum operation frequency.
Abstract translation: 分频器（2）包括具有四个晶体管对（31-34,81-84），两个栅极对（31,33,81,83）和两个锁存对（32,34,82,82）的第一晶体管电路（21） 84）并且包括具有两个晶体管对（35-36,85-86）的第二晶体管电路（22），并且包括阻抗电路（23）具有相对较低的频率范围。 通过用包括晶体管（37-40,87-90）的有源负载阻抗代替阻抗电路（23）中的现有技术的负载电阻器，分频器（2）的频率范围得到显着改善。 耦合到晶体管（37-40,87-90）的发射极的阻抗（41-44）限定了分频器（2）的工作频率范围，耦合到 晶体管（37-40,87-90）允许调谐器（2）调整最大工作频率。
-
5.发明申请HEAD END HAVING A LOW NOISE CONVERTER WITH CHANNEL PRESELECTING FREQUENCY MULTIPLEXOR 审中-公开具有通道选择频率多路复用器的低噪声转换器
公开(公告)号：WO2004030365A1
公开(公告)日：2004-04-08
申请号：PCT/IB2003/050001
申请日：2003-08-25
Inventor： HOOIJMANS, Pieter, W. , VAUCHER, Cicero, S.
IPC: H04N7/20
Abstract: A head end (7) comprises a low noise converter (2) for providing signal bands including channels to one or more user units (3). The low noise converter is arranged as a low noise channel converter (2), which includes frequency multiplexing means (6) for multiplexing one or more user pre-selected channels to the user units (3). By effecting pre-selection in the low noise channel converter (2) the connection between the head end (7) and the user units (3) only contains a single communication medium (5), generally an already installed coaxial cable (5). Wanted channels for example for watching one television program and simultaneously recording another program are pre-selected and at the side of the low noise block put on the one cable.
Abstract translation: 头端（7）包括用于向一个或多个用户单元（3）提供包括信道的信号频带的低噪声转换器（2）。 低噪声转换器被布置为低噪声信道转换器（2），其包括用于将一个或多个用户预先选择的信道复用到用户单元（3）的频率复用装置（6）。 通过在低噪声信道转换器（2）中进行预选择，头端（7）和用户单元（3）之间的连接仅包含通常已经安装的同轴电缆（5）的单个通信介质（5）。 例如用于观看一个电视节目并同时录制另一节目的通道被预先选择，并且在放置在一个电缆上的低噪声块的一侧。
-
Patent Agency Ranking
公开(公告)号：WO2004010444A1
公开(公告)日：2004-01-29
申请号：PCT/IB2003/002852
申请日：2003-06-25
Inventor： DOLMANS, Wilhelmus, M., C. , VAUCHER, Cicero, S.
IPC: H01F17/00
CPC classification number: H03B5/1847 , H01F17/0006 , H01F21/12 , H01F2021/125 , H01L27/08 , H03B5/1215 , H03B5/1231 , H03B5/124
Abstract: The invention relates to multi-band resonator circuits with inductors and capacitors. These resonator circuits are realized on integrated circuits. The inductors are realized according to the invention within one single coil comprising a center (2) tap and intermediate taps (4, 6).
Abstract translation: 本发明涉及具有电感器和电容器的多频带谐振器电路。 这些谐振电路在集成电路上实现。 电感器根据本发明在包括中心（2）抽头和中间抽头（4,6）的单个线圈内实现。
-
公开(公告)号：WO2006075307A3
公开(公告)日：2006-07-20
申请号：PCT/IB2006/050122
申请日：2006-01-13
Applicant: NXP B.V. , DARRIET, Stephane , VAUCHER, Cicero, S.
Inventor： DARRIET, Stephane , VAUCHER, Cicero, S.
Abstract: The present invention relates to a switching arrangement and method of manufacturing such an arrangement, wherein first and second series-shunt diode structures (D1/D2, D3/D4) are connected to each other in a mirrored configuration to obtain a basic switching cell. This basic switching cell can be used to build a SPDT switch which in turn can be used to build a DPDT switch or switches of higher complexity. Thereby, high isolation and low power consumption can be achieved with the additional advantage of modularity.
-
公开(公告)号：WO2004093355A1
公开(公告)日：2004-10-28
申请号：PCT/IB2004/050413
申请日：2004-04-08
Inventor： VAUCHER, Cicero, S. , STIKVOORT, Eduard, F.
IPC: H04B17/00
CPC classification number: H04B1/28 , H03J1/0008 , H03J2200/29 , H03L7/16
Abstract: A calibrating system for a receiver receiving an input signal (Rf) having an input frequency (fRf) and working in a receiving mode (R) and in a calibrating mode (C) comprising an intermediate frequency circuit (IF) coupled to a first mixer and comprising a bulk acoustic wave filter (BAW) determining the intermediate frequency (BAWf). The calibrating system further comprises a level detecting circuit (LD) coupled to the intermediate frequency circuit (IF) via a first switch (S1) in the calibrating mode (C) for determining an amplitude of the intermediate frequency signal. The receiver includes a tuning control processor (TC) coupled to the first synthesizer (LO1) and to the second synthesizer (L02) controlling the frequencies generated by said synthesizers (LO1, L02). A level detecting circuit (LD) is coupled to the intermediate frequency circuit (IF) for determining an amplitude of the intermediate frequency signal and providing a signal indicative for said amplitude to the tuning control processor (TC). The system further comprises a register (Reg) coupled to the tuning control processor (TC) for memorizing a number corresponding to the intermediate frequency (BAWf), the number being used as a correction factor for the first and second synthesizers (LO I, L02) in the receiving mode (R).
Abstract translation: 一种用于接收接收具有输入频率（fRf）并且以接收模式（R）工作的校准模式（C））的输入信号（Rf）的接收机的校准系统，包括耦合到第一混频器的中频电路（IF） 并且包括确定中间频率（BAWf）的体声波滤波器（BAW）。 校准系统还包括经由校准模式（C）中的第一开关（S1）耦合到中频电路（IF）的电平检测电路（LD），用于确定中频信号的幅度。 接收机包括耦合到第一合成器（LO1）的调谐控制处理器（TC）和控制由所述合成器（LO1，L02）产生的频率的第二合成器（L02）。 电平检测电路（LD）耦合到中频电路（IF），用于确定中频信号的幅度，并向调谐控制处理器（TC）提供指示所述振幅的信号。 该系统还包括耦合到调谐控制处理器（TC）的寄存器（Reg），用于存储对应于中间频率（BAWf）的数字，该数字被用作第一和第二合成器（LO I，L02 ）在接收模式（R）中。
-
公开(公告)号：WO2004001975A1
公开(公告)日：2003-12-31
申请号：PCT/IB2003/002732
申请日：2003-06-12
Inventor： LEENAERTS, Domincus, M., W. , VAUCHER, Cicero, S.
IPC: H03L7/099
CPC classification number: H03J1/005 , H03J1/0091 , H03L7/0891 , H03L7/099 , H03L7/10 , H03L7/197
Abstract: A tuning system (100) for receiving a radio frequency input signal included in a frequency range, the range having a maximum frequency and a minimum frequency and a plurality of non-overlapping bands, the tuning system (100) comprising a voltage-controlled oscillator (6) controlled by an analog signal (V T ) and a first binary signal (D) and being characterized in that the analog signal (V T ) is inputted to a window comparator (1), said comparator (1) having a low threshold (V L ) which is indicative for the minimum frequency and a high threshold (V H ) which is indicative for the maximum frequency.
Abstract translation: 一种调谐系统（100），用于接收包括在频率范围内的射频输入信号，所述范围具有最大频率和最小频率以及多个非重叠频带，所述调谐系统（100）包括压控振荡器 （6）由模拟信号（VT）和第一二进制信号（D）控制，并且其特征在于模拟信号（VT）被输入到窗口比较器（1），所述比较器（1）具有低阈值（ VL），其指示最小频率和指示最大频率的高阈值（VH）。
-
公开(公告)号：WO2003081916A1
公开(公告)日：2003-10-02
申请号：PCT/IB2003/000750
申请日：2003-02-26
Inventor： HOOIJMANS, Pieter, W. , VAUCHER, Cicero, S.
IPC: H04N7/20
CPC classification number: H04N21/4383 , H04H40/90 , H04N7/16 , H04N7/20 , H04N21/43615 , H04N21/43632
Abstract: A tuner for receiving a satellite broadcast signal via an antenna means, said tuner being coupled to a control unit. The tuner is characterized in that it comprises a standard bilateral digital interface for transmitting a base-band signal obtained from the received signal received via the antenna means and for receiving control signals transmitted by the control unit, said signals being transmitted/received via a first bilateral bus.
Abstract translation: 一种用于经由天线装置接收卫星广播信号的调谐器，所述调谐器耦合到控制单元。 该调谐器的特征在于它包括标准的双边数字接口，用于发送从经由天线装置接收的接收信号获得的基带信号，并且用于接收由控制单元发送的控制信号，所述信号经由第一 双边巴士
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.009 seconds)
