公开(公告)号：WO2008070053A2

公开(公告)日：2008-06-12

申请号：PCT/US2007/024797

申请日：2007-12-04

Applicant: SANDISK CORPORATION ,  ELHAMIAS, Reuven ,  ZEHAVI, David ,  BARZILAI, Roni ,  MANI, Vivek ,  STOLERO, Simon

Inventor： ELHAMIAS, Reuven ,  ZEHAVI, David ,  BARZILAI, Roni ,  MANI, Vivek ,  STOLERO, Simon

IPC: G06F15/16 ,  G06F13/00

CPC classification number: G06F13/385 ,  G06F13/4234

Abstract: Methods and systems for working around the timeout limitations of physical interface standards for detachable modules. By use of dummy data blocks to keep the bus active, the bus timeout requirements (in either direction) can be spoofed, to thereby permit more complex processing operations to be performed, which otherwise might not fit reliably within the timeout period. This permits a memory system to execute applications or process data for a time period that may exceed the bus timeout of a particular specification. A controller in the memory system deasserts the ready signal and holds the bus connecting the computer system in a "busy" state until the memory system is about to timeout. During a write operation, the controller receives dummy data blocks from the computer system before the write bus timeout period expires, causing the bus timeout period to be reset. During a read operation, the controller sends dummy data blocks to the computer system before the read bus timeout period expires, causing the bus timeout period to be reset.

Abstract translation: 用于解决可拆卸模块的物理接口标准的超时限制的方法和系统。 通过使用伪数据块来保持总线活动，可以欺骗总线超时要求（在任一方向），从而允许执行更复杂的处理操作，否则可能在超时时间段内不可靠地适应。 这允许存储器系统在可能超过特定规范的总线超时的时间段内执行应用程序或处理数据。 存储器系统中的控制器取消准备就绪信号并将连接计算机系统的总线保持在“忙碌” 直到内存系统即将超时。 在写入操作期间，控制器在写入总线超时周期到期之前从计算机系统接收虚拟数据块，导致总线超时周期被重置。 在读操作期间，控制器在读总线超时周期到期之前向计算机系统发送伪数据块，导致总线超时周期被重置。

公开(公告)号：WO2008070053A3

公开(公告)日：2008-08-21

申请号：PCT/US2007024797

申请日：2007-12-04

Applicant: SANDISK CORP ,  ELHAMIAS REUVEN ,  ZEHAVI DAVID ,  BARZILAI RONI ,  MANI VIVEK ,  STOLERO SIMON

Inventor： ELHAMIAS REUVEN ,  ZEHAVI DAVID ,  BARZILAI RONI ,  MANI VIVEK ,  STOLERO SIMON

IPC: G06F15/16 ,  G06F13/00

CPC classification number: G06F13/385 ,  G06F13/4234

Abstract: Methods and systems for working around the timeout limitations of physical interface standards for detachable modules. By use of dummy data blocks to keep the bus active, the bus timeout requirements (in either direction) can be spoofed, to thereby permit more complex processing operations to be performed, which otherwise might not fit reliably within the timeout period. This permits a memory system to execute applications or process data for a time period that may exceed the bus timeout of a particular specification. A controller in the memory system deasserts the ready signal and holds the bus connecting the computer system in a "busy" state until the memory system is about to timeout. During a write operation, the controller receives dummy data blocks from the computer system before the write bus timeout period expires, causing the bus timeout period to be reset. During a read operation, the controller sends dummy data blocks to the computer system before the read bus timeout period expires, causing the bus timeout period to be reset.

Abstract translation: 解决可拆卸模块物理接口标准超时限制的方法和系统。 通过使用虚拟数据块来保持总线有效，可以欺骗总线超时要求（在任一方向上），从而允许执行更复杂的处理操作，否则在超时时间段内可能不可靠。 这允许存储器系统在可能超过特定规范的总线超时的时间段内执行应用或处理数据。 存储器系统中的控制器取消准备就绪信号并保持连接计算机系统处于“忙”状态的总线，直到存储器系统即将超时。 在写入操作期间，控制器在写入总线超时时间到期之前从计算机系统接收虚拟数据块，导致总线超时周期被复位。 在读操作期间，控制器在读总线超时时间到期之前，向计算机系统发送伪数据块，导致总线超时时间被重置。

公开(公告)号：WO2006017152A1

公开(公告)日：2006-02-16

申请号：PCT/US2005/024201

申请日：2005-07-07

Applicant: SANDISK CORPORATION ,  STOLERO, Simon ,  HOLTZMAN, Micky ,  PINTO, Yosi ,  ELHAMIAS, Reuven ,  AZARI, Meiri

Inventor： STOLERO, Simon ,  HOLTZMAN, Micky ,  PINTO, Yosi ,  ELHAMIAS, Reuven ,  AZARI, Meiri

IPC: G06F11/267

CPC classification number: G06F11/267

Abstract: In a non-volatile memory system, test data may be retrieved by means of a circuit without the help of firmware. The circuit is triggered into action when it detects an abnormality in the processor or host interface. In such event, it formats the self test or status signals from the various blocks in the non-volatile memory system controller and sends a test message to the outside world without the assistance of the system processor or interface controller. When implemented in memory systems with multiple data lines, only one of the data lines may be utilized for such purpose, thereby allowing the testing to be performed while the system is still performing data transfer. Preferably, the system includes the test mode communication controller, which can select between a test channel and a host interface channel for the test message transfer so that the same testing may be performed when the memory system is in the test package as well as in an encapsulated package. The test message is transmitted repeatedly and the test message is structured so that it is easier for the receiver host to decipher the message without a handshake with the memory system. A communication controller preferably detects whether any of the communication channels is not used by the controller of a non-volatile memory system for sending signals and sends diagnostic signals through such channel.

Abstract translation: 在非易失性存储器系统中，测试数据可以通过电路在没有固件的帮助下检索。 当检测到处理器或主机接口中的异常时，电路被触发成动作。 在这种情况下，它会从非易失性存储器系统控制器中的各个块格式化自检或状态信号，并在没有系统处理器或接口控制器的帮助的情况下向外界发送测试消息。 当在具有多个数据线的存储器系统中实现时，只有一个数据线可以用于此目的，从而允许在系统仍然执行数据传输时执行测试。 优选地，该系统包括测试模式通信控制器，其可以在测试信道和用于测试消息传送的主机接口信道之间进行选择，使得当存储器系统处于测试包中时也可以执行相同的测试 封装包装。 测试消息被重复发送，并且测试消息被构造成使得接收者主机更容易解密消息而不与存储器系统进行握手。 通信控制器优选地检测用于发送信号的非易失性存储器系统的控制器是否没有使用任何通信信道，并且通过这样的信道发送诊断信号。