公开(公告)号：WO2007033322A3

公开(公告)日：2007-05-10

申请号：PCT/US2006035840

申请日：2006-09-13

Applicant: SANDISK CORP ,  HOLTZMAN MICHAEL ,  BARZILAI RON ,  ELHAMIAS REUVEN ,  COHEN NIV

Inventor： HOLTZMAN MICHAEL ,  BARZILAI RON ,  ELHAMIAS REUVEN ,  COHEN NIV

IPC: G06F21/57

CPC classification number: G06F21/57

Abstract: A memory system comprises an encryption engine implemented in the hardware of a controller. In starting up the memory system, a boot strapping mechanism is implemented wherein a first portion of firmware when executed pulls in another portion of firmware to be executed. The hardware of the encryption engine is used to verify the integrity of at least the first portion of the firmware. Therefore, only the firmware that is intended to run the system will be executed.

Abstract translation: 存储器系统包括在控制器的硬件中实现的加密引擎。 在启动存储器系统时，实现了引导捆扎机制，其中当执行时固件的第一部分拉出要执行的固件的另一部分。 加密引擎的硬件用于验证至少固件的第一部分的完整性。 因此，只有打算运行系统的固件才能执行。

公开(公告)号：WO2005062248A1

公开(公告)日：2005-07-07

申请号：PCT/US2004/040952

申请日：2004-12-07

Applicant: SANDISK CORPORATION ,  ZER, Aviad ,  ELHAMIAS, Reuven

Inventor： ZER, Aviad ,  ELHAMIAS, Reuven

IPC: G06K19/077

CPC classification number: G06K19/07732 ,  G06F13/28 ,  G06F13/385 ,  G06K19/077 ,  G06K19/07741 ,  Y02D10/14 ,  Y02D10/151

Abstract: A removable electronic circuit card (33) having multiple modules, such a memory module with a non-volatile mass storage memory and a separate input-output (37a) module, where data transfers may be made through the a first module directly to and from the another in a direct memory access (DMA) type transfer when the card is inserted into the host system (31) but without having to pass the data through the host system. Once the host gives a DMA command, the data transfer is accomplished independently of the host system, except for the host supplying power and possibly a clock signal and other like support, during such a data transfer directly with card. The data for the transfer can be communicated between the input-output module and the exterior device through either wireless or an electrical connection means.

Abstract translation: 具有多个模块的可拆卸电子电路卡（33），具有非挥发性大容量存储器的存储器模块和单独的输入 - 输出（37a）模块，其中可以通过第一模块直接进行数据传输 当卡被插入主机系统（31）但不必通过主机系统传递数据时，直接存储器访问（DMA）类型中的另一个传送。 一旦主机给出DMA命令，数据传输是独立于主机系统完成的，除了主机提供电源以及可能的时钟信号和其他类似的支持之外，在这种数据传输过程中直接使用卡。 用于传送的数据可以通过无线或电连接装置在输入 - 输出模块和外部设备之间进行通信。

公开(公告)号：WO2012020292A1

公开(公告)日：2012-02-16

申请号：PCT/IB2011/001748

申请日：2011-07-28

Applicant: SANDISK IL LTD ,  DOLGUNOV, Boris ,  ELHAMIAS, Reuven ,  COHEN, Ehud

Inventor： DOLGUNOV, Boris ,  ELHAMIAS, Reuven ,  COHEN, Ehud

IPC: G06F21/00

CPC classification number: G06F9/4406 ,  G06F21/123 ,  G06F21/575 ,  G06F21/72 ,  G06F21/85

Abstract: A host device and method for securely booting the host device with operating system code loaded from a storage device are provided. In one embodiment, a host device is in communication with a storage device having a private memory area storing boot loader code and a public memory area storing operating system code. The host device instructs the storage device to initiate a boot mode and receives the boot loader code from the storage device. The host device executes the boot loader code which performs a security check and executes the operating system code loaded from the storage device only if the security check is successful.

Abstract translation: 提供了一种用于使用从存储设备加载的操作系统代码安全地引导主机设备的主机设备和方法。 在一个实施例中，主机设备与具有存储引导加载程序代码的专用存储区域和存储操作系统代码的公共存储区域的存储设备通信。 主机设备指示存储设备启动引导模式，并从存储设备接收引导加载程序代码。 主机设备执行执行安全检查的引导加载程序代码，并且只有在安全检查成功的情况下才执行从存储设备加载的操作系统代码。

公开(公告)号：WO2006017152A1

公开(公告)日：2006-02-16

申请号：PCT/US2005/024201

申请日：2005-07-07

Applicant: SANDISK CORPORATION ,  STOLERO, Simon ,  HOLTZMAN, Micky ,  PINTO, Yosi ,  ELHAMIAS, Reuven ,  AZARI, Meiri

Inventor： STOLERO, Simon ,  HOLTZMAN, Micky ,  PINTO, Yosi ,  ELHAMIAS, Reuven ,  AZARI, Meiri

IPC: G06F11/267

CPC classification number: G06F11/267

Abstract: In a non-volatile memory system, test data may be retrieved by means of a circuit without the help of firmware. The circuit is triggered into action when it detects an abnormality in the processor or host interface. In such event, it formats the self test or status signals from the various blocks in the non-volatile memory system controller and sends a test message to the outside world without the assistance of the system processor or interface controller. When implemented in memory systems with multiple data lines, only one of the data lines may be utilized for such purpose, thereby allowing the testing to be performed while the system is still performing data transfer. Preferably, the system includes the test mode communication controller, which can select between a test channel and a host interface channel for the test message transfer so that the same testing may be performed when the memory system is in the test package as well as in an encapsulated package. The test message is transmitted repeatedly and the test message is structured so that it is easier for the receiver host to decipher the message without a handshake with the memory system. A communication controller preferably detects whether any of the communication channels is not used by the controller of a non-volatile memory system for sending signals and sends diagnostic signals through such channel.

Abstract translation: 在非易失性存储器系统中，测试数据可以通过电路在没有固件的帮助下检索。 当检测到处理器或主机接口中的异常时，电路被触发成动作。 在这种情况下，它会从非易失性存储器系统控制器中的各个块格式化自检或状态信号，并在没有系统处理器或接口控制器的帮助的情况下向外界发送测试消息。 当在具有多个数据线的存储器系统中实现时，只有一个数据线可以用于此目的，从而允许在系统仍然执行数据传输时执行测试。 优选地，该系统包括测试模式通信控制器，其可以在测试信道和用于测试消息传送的主机接口信道之间进行选择，使得当存储器系统处于测试包中时也可以执行相同的测试 封装包装。 测试消息被重复发送，并且测试消息被构造成使得接收者主机更容易解密消息而不与存储器系统进行握手。 通信控制器优选地检测用于发送信号的非易失性存储器系统的控制器是否没有使用任何通信信道，并且通过这样的信道发送诊断信号。

公开(公告)号：WO2006014791A2

公开(公告)日：2006-02-09

申请号：PCT/US2005/025983

申请日：2005-07-20

Applicant: SANDISK CORPORATION ,  ELHAMIAS, Reuven ,  TOMLIN, Andrew ,  BREWER, Wesley G. ,  PINTO, Yosi ,  HOLTZMAN, Micky

Inventor： ELHAMIAS, Reuven ,  TOMLIN, Andrew ,  BREWER, Wesley G. ,  PINTO, Yosi ,  HOLTZMAN, Micky

IPC: G06F13/38

CPC classification number: G06F3/0607 ,  G06F3/0632 ,  G06F3/0679 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory card that adapts its operation according to the application to which it applied or the conditions under which it is operated. This allows the card to dynamical self optimize. In a first set of embodiments, the card uses host profiling where it will learn about the host during host-card interactions and the card's controller will optimize its algorithms accordingly. In another set of embodiments, the host and card will report to one another their capabilities for a quality of service negotiation. A further set of embodiments allows the storage device to memorize access sequences issued by the host under various predefined conditions, such as host reset or a power on boot sequence. The storage device can use this information to optimize operation for the expected commands. On deviation from an expected sequence, the device would memorize the new command sequence and save it, thus operating in a self-adaptive manner.

Abstract translation: 一种根据其应用的应用或其运行条件来适应其操作的存储卡。 这样可以让卡片进行动态自我优化。 在第一组实施例中，卡使用主机分析，其中将在主机卡交互期间了解主机，并且卡的控制器将相应地优化其算法。 在另一组实施例中，主机和卡将彼此报告其服务质量协商的能力。 另一组实施例允许存储设备在诸如主机复位或引导顺序的电源的各种预定条件下存储由主机发出的访问序列。 存储设备可以使用该信息来优化预期命令的操作。 在偏离预期序列时，设备将记忆新的命令序列并保存，从而以自适应的方式运行。

公开(公告)号：WO2008070053A3

公开(公告)日：2008-08-21

申请号：PCT/US2007024797

申请日：2007-12-04

Applicant: SANDISK CORP ,  ELHAMIAS REUVEN ,  ZEHAVI DAVID ,  BARZILAI RONI ,  MANI VIVEK ,  STOLERO SIMON

Inventor： ELHAMIAS REUVEN ,  ZEHAVI DAVID ,  BARZILAI RONI ,  MANI VIVEK ,  STOLERO SIMON

IPC: G06F15/16 ,  G06F13/00

CPC classification number: G06F13/385 ,  G06F13/4234

Abstract: Methods and systems for working around the timeout limitations of physical interface standards for detachable modules. By use of dummy data blocks to keep the bus active, the bus timeout requirements (in either direction) can be spoofed, to thereby permit more complex processing operations to be performed, which otherwise might not fit reliably within the timeout period. This permits a memory system to execute applications or process data for a time period that may exceed the bus timeout of a particular specification. A controller in the memory system deasserts the ready signal and holds the bus connecting the computer system in a "busy" state until the memory system is about to timeout. During a write operation, the controller receives dummy data blocks from the computer system before the write bus timeout period expires, causing the bus timeout period to be reset. During a read operation, the controller sends dummy data blocks to the computer system before the read bus timeout period expires, causing the bus timeout period to be reset.

Abstract translation: 解决可拆卸模块物理接口标准超时限制的方法和系统。 通过使用虚拟数据块来保持总线有效，可以欺骗总线超时要求（在任一方向上），从而允许执行更复杂的处理操作，否则在超时时间段内可能不可靠。 这允许存储器系统在可能超过特定规范的总线超时的时间段内执行应用或处理数据。 存储器系统中的控制器取消准备就绪信号并保持连接计算机系统处于“忙”状态的总线，直到存储器系统即将超时。 在写入操作期间，控制器在写入总线超时时间到期之前从计算机系统接收虚拟数据块，导致总线超时周期被复位。 在读操作期间，控制器在读总线超时时间到期之前，向计算机系统发送伪数据块，导致总线超时时间被重置。

公开(公告)号：WO2007047110A1

公开(公告)日：2007-04-26

申请号：PCT/US2006/038808

申请日：2006-10-04

Applicant: SANDISK CORPORATION ,  GOROBETS, Sergey, Anatolievich ,  ELHAMIAS, Reuven ,  GONZALEZ, Carlos, J. ,  CONLEY, Kevin, M.

Inventor： GOROBETS, Sergey, Anatolievich ,  ELHAMIAS, Reuven ,  GONZALEZ, Carlos, J. ,  CONLEY, Kevin, M.

IPC: G06F11/10 ,  G11C29/00

CPC classification number: G06F11/106 ,  G06F11/1068 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/76

Abstract: In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase. Data is rewritten when severe errors are found during read operations. Portions of data are corrected and copied within the time limit for read operation. Corrected portions are written to dedicated blocks.

Abstract translation: 为了保持存储在闪速存储器中的数据的完整性，其易于被存储器的相邻区域中的操作干扰，干扰事件导致在变得如此损坏之前读取，校正和重新写入数据，使得有效数据不能 被收回 当存储系统具有执行其他高优先级操作时，通过推迟执行某些纠正措施来平衡维护数据完整性和系统性能的有时冲突的需求。 在使用非常大的擦除单位的存储器系统中，以与有效地重写远远小于擦除单位的容量的数据量相一致的方式执行校正处理。 在读取操作期间发现严重错误时，重写数据。 部分数据在读取操作的时限内得到纠正和复制。 校正的部分被写入专用块。

公开(公告)号：WO2007033322A2

公开(公告)日：2007-03-22

申请号：PCT/US2006/035840

申请日：2006-09-13

Applicant: SANDISK CORPORATION ,  HOLTZMAN, Michael ,  BARZILAI, Ron ,  ELHAMIAS, Reuven ,  COHEN, Niv

Inventor： HOLTZMAN, Michael ,  BARZILAI, Ron ,  ELHAMIAS, Reuven ,  COHEN, Niv

IPC: G06F21/57

CPC classification number: G06F21/57

Abstract: A memory system comprises an encryption engine implemented in the hardware of a controller. In starting up the memory system, a boot strapping mechanism is implemented wherein a first portion of firmware when executed pulls in another portion of firmware to be executed. The hardware of the encryption engine is used to verify the integrity of at least the first portion of the firmware. Therefore, only the firmware that is intended to run the system will be executed.

Abstract translation: 存储器系统包括在控制器的硬件中实现的加密引擎。 在启动存储器系统时，实现引导捆扎机制，其中第一部分固件在被执行时牵引要执行的另一部分固件。 加密引擎的硬件被用来验证至少第一部分固件的完整性。 因此，只有用于运行系统的固件才会被执行。

公开(公告)号：WO2012170141A1

公开(公告)日：2012-12-13

申请号：PCT/US2012/037068

申请日：2012-05-09

Applicant: SANDISK TECHNOLOGIES INC. ,  ELHAMIAS, Reuven

Inventor： ELHAMIAS, Reuven

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0866 ,  G06F2212/214 ,  G06F2212/221 ,  Y02D10/13

Abstract: A data storage device includes a controller (106), a non-volatile mem¬ ory (104), and a buffer (108) accessible to the controller. The buffer is configured to store data (154, 156) retrieved from the non-volatile memory to be accessible to a host device (130) in response to receiv¬ ing from the host device one or more requests (132) for read access to the non-volatile memory. The controller is configured to read an in¬ dicator (110) of cached data in response to receiving a request for read access to the non-volatile memory. The request includes a data identifier (138). In response to the indicator of cached data not indi¬ cating that data corresponding to the data identifier is in the buffer, the controller is configured to retrieve data (144) corresponding to the data identifier as well as additional data (146) from the non-volatile memory and to write the data corresponding to the data identifier and the additional data to the buffer.

Abstract translation: 数据存储设备包括控制器（106），非易失性存储器（104）和可由控制器访问的缓冲器（108）。 缓冲器被配置为存储从非易失性存储器检索的数据（154,156），以响应于从主机设备接收一个或多个用于读访问的请求（132），主机设备（130）可访问 非易失性存储器。 响应于接收到对非易失性存储器的读取访问的请求，控制器被配置为读取缓存数据的引用（110）。 请求包括数据标识符（138）。 响应于缓存数据的指示符，未指示对应于数据标识符的数据在缓冲器中，控制器被配置为从非数据标识符检索对应于数据标识符的数据（144）以及附加数据（146） 并将与数据标识符和附加数据相对应的数据写入缓冲器。

公开(公告)号：WO2007118034A3

公开(公告)日：2009-08-13

申请号：PCT/US2007065679

申请日：2007-03-30

Applicant: SANDISK CORP ,  ELHAMIAS REUVEN ,  MANI VIVEK VENKATRAMEN ,  COHEN NIV

Inventor： ELHAMIAS REUVEN ,  MANI VIVEK VENKATRAMEN ,  COHEN NIV

IPC: H04L9/32

CPC classification number: H04L9/0637 ,  G06F11/1666 ,  G06F11/2053 ,  H04L9/0643

Abstract: When cipher block chaining encryption/decryption is employed, write fault recovery is accomplished by storing information useful for the writing of cipher block chaining processed data before it is written to storage cells. Hence when write failure is discovered, this information stored can be retrieved for rewriting the data to the cells. Preferably, the information stored includes security configuration information for cipher block chaining processing a unit of data.

Abstract translation: 当使用密码块链接加密/解密时，通过在将密码块链接处理的数据写入存储单元之前存储对写入密码块链接处理的数据有用的信息来实现写入故障恢复。 因此，当发现写入失败时，可以检索存储的信息以将数据重写到单元。 优选地，存储的信息包括用于密码块链接处理数据单元的安全配置信息。