Abstract:
The circuit construction of a memory tester equipped with a ROM expected value memory is simplified. Data read out from a tested memory (200) and expected value data from a pattern generator (11) are inputted to a first logical comparator (26) for logically comparing them. The comparison result of the first logical comparator (26) is applied to one of the input terminals of a second logical comparator (28). ROM expected value data read out from the ROM expected value memory (16) is applied to the other input terminal of the second logical comparator (28). The first logical comparator (26) compares logically the data read out from a RAM under test, and the second logical comparator (28) compares logically the data read out from a ROM under test.
Abstract:
The circuit construction of a memory tester having a mask pattern memory is simplified. Mask pattern data read out of the mask pattern memory (11) are, without being converted into a bit arrangement corresponding to the arrangement of the terminals of a memory (200) under test, supplied directly to a masking circuit (113). Provisional fail data of the bit arrangement are given from a logic comparator (107) to a fail data selector (108) which controls the flow of the fail data whose arrangement is converted into a bit arrangement in order of weighting and supplies the fail data to the masking circuit, by which the writing into a defect analysis memory (109) is masked.
Abstract:
A method and equipment for gasification and burning of solid waste in which the solid waste is subjected to thermal decomposition and gasification at 450 DEG -650 DEG C in a fluidized bed of a fluidized bed gasification furnace, the resultant waste being subjected to melt combustion at 1200 DEG -1500 DEG C in a melt combustion furnace in a subsequent stage, whereby the ash is turned into fused slag. At least one of oxygen, vapor and air is selected as a gas supplied to the fluidized bed in the fluidized bed gasification furnace. The quantity of oxygen in the gas supplied to the fluidized bed is set to 10-30 % of a quantity of theoretical combustion oxygen. The following whirling movements of a fluidized medium are generated. The fluidized medium flows down as it is fluidized in a slow fluidized bed in a central portion of a furnace bottom, flows up as it is fluidized in an active fluidized bed in a peripheral portion of the furnace bottom, flows from a central portion to a peripheral portion in a lower portion of the fluidized bed and from a peripheral portion to a central portion in an upper portion of the fluidized bed as the fluidized medium is fluidized, and flows from a central portion to a peripheral portion in the lower portion of the fluidized bed as the fluidized medium is fluidized. The melt combustion furnace is of a whirling flow type.
Abstract:
A treating method for solid wastes such as municipal wastes, solidified fuel and biomass wastes comprising the steps of thermally decomposing solid wastes for gasification in a fluidized gasification oven (1), and burning the wastes so decomposed and gasified at a high temperature in a fusion oven (9), wherein a primary combustion in a fluidized portion (4) of a gasifying oven is effected within 50 DEG C plus/minus 600 DEG C, wherein a secondary combustion in a free board portion (3) of the gasifying oven is effected within 75 DEG C plus/minus 725 DEG C, wherein a third combustion in the fusion oven (9) is carried out at temperatures 50 to 100 DEG C higher than the fused and fluidized temperature of ash, and wherein the oxygen ratio (a ratio of the supplied oxygen amount to the theoretical combustion oxygen amount) is set at 0.1 to 0.3, the oxygen ratio in the secondary combustion at 0.05 to 0.1, the oxygen ratio in the third combustion at 0.9 to 1.1 and the total oxygen ratio at about 1.3.
Abstract:
This invention makes it possible to improve the speed of data transfer between LSIs operating by the same reference clock CKs. An internal clock CK1 of an LSI (14) is outputted from a circuit (41) to a clock line (42) at the timing at which data is outputted from the LSI (14) to a signal line (22). In an LSI (15), the clock CK1 is received by a circuit (43), and the data on the signal line (22) is fetched to FF (45) in response to the clock CK1. The phase difference between the clock CK1 and the internal clock CK2 of the LSI (15) is removed from the output data of FF (45) by a circuit (46), which receives or outputs the data at a desired time.