公开(公告)号：WO2007098305A3

公开(公告)日：2008-03-13

申请号：PCT/US2007060843

申请日：2007-01-22

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  GE LIXIN ,  VEERARAGHAVAN SURYA

Inventor： MATHEW LEO ,  GE LIXIN ,  VEERARAGHAVAN SURYA

IPC: H01L27/12

CPC classification number: H01L29/78615 ,  H01L29/785

Abstract: A method for making a semiconductor device includes patterning a semiconductor layer (14), overlying an insulator layer (12), to create a first active region (28) and a second active region (30), wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure (26) over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

Abstract translation: 制造半导体器件的方法包括图案化覆盖绝缘体层（12）的半导体层（14），以形成第一有源区（28）和第二有源区（30），其中第一有源区为 与第二有源区不同的高度，并且其中第一有源区的至少一部分具有第一导电类型，并且第二有源区的至少一部分具有与至少一个沟道中的第一导电类型不同的第二导电类型 半导体器件的区域。 该方法还包括在第一有源区域和第二有源区域的至少一部分上形成栅极结构（26）。 该方法还包括去除半导体器件的一侧上的第二有源区的一部分。

公开(公告)号：WO2005060464A3

公开(公告)日：2005-11-17

申请号：PCT/US2004037760

申请日：2004-11-12

Applicant: FREESCALE SEMICONDUCTOR INC ,  VEERARAGHAVAN SURYA ,  DU YANG ,  WORKMAN GLENN O

Inventor： VEERARAGHAVAN SURYA ,  DU YANG ,  WORKMAN GLENN O

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/78615

Abstract: A method for forming a silicon-on-insulator transistor (80) includes forming an active region (82) overlying an insulating layer (122), wherein a portion of the active region provides an intrinsic body region (126). A body tie access region (128) is also formed within the active region, overlying the insulating layer and laterally disposed adjacent the intrinsic body region, making electrical contact to the intrinsic body region. A gate electrode (134) is formed overlying the intrinsic body region for providing electrical control of the intrinsic body region, the gate electrode extending over a portion (137) of the body tie access region. The gate electrode is formed having a substantially constant gate length (88) along its entire width overlying the intrinsic body region and the body tie access region to minimize parasitic capacitance and gate electrode leakage. First and second current electrodes (98,100) are formed adjacent opposite sides of the intrinsic body region. In addition, a body tie diffusion (130) is formed within the active region and laterally offset from the body tie access region and electrically coupled to the body tie access region.

Abstract translation: 一种用于形成绝缘体上硅晶体管（80）的方法包括形成覆盖绝缘层（122）的有源区（82），其中有源区的一部分提供本征体区（126）。 在主动区域内还形成有身体接近区域（128），覆盖绝缘层并且横向设置在本体体区域附近，使得与本体区域电接触。 栅极电极（134）形成在本体体区域的上方，用于提供本征体区域的电控制，栅电极延伸到身体接头进入区域的一部分（137）上。 栅电极形成为具有基本上恒定的栅极长度（88），其整个宽度覆盖本征体区域和主体接合区域，以最小化寄生电容和栅电极泄漏。 第一和第二电流电极（98,100）形成在本体体区域的相对侧附近。 此外，在有源区域内形成主体连接扩散（130）并且横向偏离身体束带进入区域并且电耦合到身体接头进入区域。

公开(公告)号：WO2005060464A2

公开(公告)日：2005-07-07

申请号：PCT/US2004/037760

申请日：2004-11-12

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  VEERARAGHAVAN, Surya ,  DU, Yang ,  WORKMAN, Glenn, O.

Inventor： VEERARAGHAVAN, Surya ,  DU, Yang ,  WORKMAN, Glenn, O.

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/78615

Abstract: A method for forming a silicon-on-insulator transistor (80) includes forming an active region (82) overlying an insulating layer (122), wherein a portion of the active region provides an intrinsic body region (126). A body tie access region (128) is also formed within the active region, overlying the insulating layer and laterally disposed adjacent the intrinsic body region, making electrical contact to the intrinsic body region. A gate electrode (134) is formed overlying the intrinsic body region for providing electrical control of the intrinsic body region, the gate electrode extending over a portion (137) of the body tie access region. The gate electrode is formed having a substantially constant gate length (88) along its entire width overlying the intrinsic body region and the body tie access region to minimize parasitic capacitance and gate electrode leakage. First and second current electrodes (98,100) are formed adjacent opposite sides of the intrinsic body region. In addition, a body tie diffusion (130) is formed within the active region and laterally offset from the body tie access region and electrically coupled to the body tie access region.

Abstract translation: 一种用于形成绝缘体上硅晶体管（80）的方法包括形成覆盖绝缘层（122）的有源区（82），其中有源区的一部分提供本征体区 （126）。 在活性区域内还形成体引出通路区域（128），覆盖绝缘层并横向设置在本体区域附近，与本征体区域形成电接触。 形成覆盖本征体区的栅电极（134），用于提供本征体区的电控制，栅电极在本体连接存取区的一部分（137）上延伸。 形成的栅电极具有沿其整个宽度的基本上恒定的栅极长度（88），覆盖本征体区和本体连接存取区，以最小化寄生电容和栅电极泄漏。 第一和第二电流电极（98,100）形成在本征体区的相对侧附近。 此外，体连接扩散（130）形成在有源区内并且从体连接接入区横向偏移并电耦合到体连接接入区。

公开(公告)号：WO2007098305A2

公开(公告)日：2007-08-30

申请号：PCT/US2007/060843

申请日：2007-01-22

Applicant: FREESCALE SEMICONDUCTOR INC. ,  MATHEW, Leo ,  GE, Lixin ,  VEERARAGHAVAN, Surya

Inventor： MATHEW, Leo ,  GE, Lixin ,  VEERARAGHAVAN, Surya

IPC: H01L27/12

CPC classification number: H01L29/78615 ,  H01L29/785

Abstract: A method for making a semiconductor device includes patterning a semiconductor layer (14), overlying an insulator layer (12), to create a first active region (28) and a second active region (30), wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure (26) over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

Abstract translation: 制造半导体器件的方法包括图案化覆盖绝缘体层（12）的半导体层（14），以形成第一有源区（28）和第二有源区（30），其中第一有源区为 与第二有源区不同的高度，并且其中第一有源区的至少一部分具有第一导电类型，并且第二有源区的至少一部分具有与至少一个沟道中的第一导电类型不同的第二导电类型 半导体器件的区域。 该方法还包括在第一有源区域和第二有源区域的至少一部分上形成栅极结构（26）。 该方法还包括去除半导体器件一侧上的第二有源区的一部分。