公开(公告)号：WO2009046114A2

公开(公告)日：2009-04-09

申请号：PCT/US2008/078460

申请日：2008-10-01

Applicant: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC. ,  FOSSUM, Jerry, G. ,  MATHEW, Leo ,  SADD, Michael ,  TRIVEDI, Vishal, P.

Inventor： FOSSUM, Jerry, G. ,  MATHEW, Leo ,  SADD, Michael ,  TRIVEDI, Vishal, P.

IPC: H01L21/8242

CPC classification number: H01L27/108 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L27/10826 ,  H01L29/7841 ,  H01L29/785

Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded- DRAM applications. Further embodiments pertain to a floating-body/ gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.

Abstract translation: 实施例涉及用于嵌入式DRAM应用的双晶体管（2T）浮体单元（FBC）。 除了更好的信号余量，更长的数据保持和更高的存储器密度之外，其它实施例涉及浮体/栅极单元（FBGC），其产生功率损耗的降低。

公开(公告)号：WO2007120293A3

公开(公告)日：2008-11-06

申请号：PCT/US2006061283

申请日：2006-11-28

Applicant: FREESCALE SEMICONDUCTOR INC ,  BURNETT JAMES D ,  MATHEW LEO ,  MIN BYOUNG W

Inventor： BURNETT JAMES D ,  MATHEW LEO ,  MIN BYOUNG W

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A process for forming an electronic device can include forming a semiconductor fin (18) of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin (934) is shortened to a second height. In accordance with specific embodiment a second semiconductor fin (932) can be formed, each of the first (934) and the second (932) semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second (932) and a third semiconductor fin (938) can be formed, each of the first (934), the second (932) and the third semiconductor fins (938) having a different height representing a channel width.

Abstract translation: 一种用于形成电子器件的方法可以包括形成用于鳍型结构的第一高度的半导体鳍片（18），并且去除半导体鳍片的一部分，使得半导体鳍片（934）被缩短到第二高度。 根据具体实施例，可以形成第二半导体翅片（932），第一（934）和第二（932）半导体鳍片中的每一个具有表示通道宽度的不同高度。 根据另一个具体实施例，可以形成第二（932）和第三半导体翅片（938），第一（934），第二（932）和第三半导体翅片（938）中的每一个具有不同的高度， 信道宽度。

公开(公告)号：WO2007050288A3

公开(公告)日：2008-01-03

申请号：PCT/US2006039651

申请日：2006-10-10

Applicant: FREESCALE SEMICONDUCTOR INC ,  MIN BYOUNG W ,  BURNETT JAMES D ,  MATHEW LEO

Inventor： MIN BYOUNG W ,  BURNETT JAMES D ,  MATHEW LEO

IPC: H01L21/4763 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for making a semiconductor device (10) is provided. The method includes forming a first transistor (94) with a vertical active region (56) and a horizontal active region (54) extending on both sides of the vertical active region (56). The method further includes forming a second transistor (96) with a vertical active region (58). The method further includes forming a third transistor (98) with a vertical active region (60) and a horizontal active region (54) extending on only one side of the vertical active region (60).

Abstract translation: 提供一种制造半导体器件（10）的方法。 该方法包括形成具有在垂直有源区（56）的两侧延伸的垂直有源区（56）和水平有源区（54）的第一晶体管（94）。 该方法还包括形成具有垂直有源区（58）的第二晶体管（96）。 该方法还包括形成具有仅在垂直有源区域（60）的一侧上延伸的垂直有源区域（60）和水平有源区域（54）的第三晶体管（98）。

公开(公告)号：WO2007047164A3

公开(公告)日：2007-09-27

申请号：PCT/US2006039177

申请日：2006-10-04

Applicant: FREESCALE SEMICONDUCTOR INC ,  KALPAT SRIRAM S ,  MATHEW LEO ,  MOOSA MOHAMED S ,  SADD MICHAEL A ,  SANCHEZ HECTOR

Inventor： KALPAT SRIRAM S ,  MATHEW LEO ,  MOOSA MOHAMED S ,  SADD MICHAEL A ,  SANCHEZ HECTOR

IPC: H03B1/00

CPC classification number: H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0995

Abstract: A voltage controlled oscillator (VCO) (40) has a plurality (42, 44, 46) of series-connected inverters. Within each inverter a first transistor (48) has a first current electrode coupled to a first power supply voltage terminal (VDD), a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series connected inverters, and a second control electrode for receiving a first bias signal. A second transistor (50) has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal (Vss), and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal (VGp, VPP OR DNP) to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

Abstract translation: 压控振荡器（VCO）（40）具有多个（42,44,46）串联逆变器。 在每个逆变器内，第一晶体管（48）具有耦合到第一电源电压端子（VDD）的第一电流电极，第二电流电极，耦合到多个串联连接的逆变器中的另一个反相器的输出端子的第一控制电极 以及用于接收第一偏置信号的第二控制电极。 第二晶体管（50）具有耦合到第一晶体管的第二电流电极的第一电流电极，耦合到第二电源电压端子（Vss）的第二电流电极，以及耦合到第一控制电极的第一控制电极的第一控制电极 第一个晶体管。 每个逆变器的第一晶体管的第二控制电极接收相同或分开的模拟控制信号（VGp，VPP或DNP），以调整其第一晶体管的阈值电压以影响VCO信号的频率和相位。

公开(公告)号：WO2007050317A2

公开(公告)日：2007-05-03

申请号：PCT/US2006040019

申请日：2006-10-11

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  MORA RODE R

Inventor： MATHEW LEO ,  MORA RODE R

IPC: H01L21/338

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for creating an inverse T field effect transistor (10) is provided. The method includes creating a horizontal active region (14) and a vertical active region (16) on a substrate (12). The method further comprises forming a sidewall spacer (22) on a first side of the vertical active region and a second side of the vertical active region (16). The method further includes removing a portion of the horizontal active region (14), which is not covered by the sidewall spacer (22). The method further includes removing the sidewall spacer (22). The method further includes forming a gate dielectric (26) over at least a first part of the horizontal active region (14) and at least a first part of the vertical active region (16). The method further includes forming a gate electrode (28) over the gate dielectric (26). The method further includes forming a source region (30) and a drain region (32) over at least a second part of the horizontal active region and at least a second part of the vertical active region (16).

Abstract translation: 提供了一种用于创建逆T型场效应晶体管（10）的方法。 该方法包括在衬底（12）上创建水平有源区域（14）和垂直有源区域（16）。 该方法进一步包括在垂直有源区的第一侧和垂直有源区（16）的第二侧上形成侧壁间隔物（22）。 该方法还包括去除没有被侧壁间隔物（22）覆盖的水平有源区（14）的一部分。 该方法还包括去除侧壁间隔件（22）。 该方法还包括在水平有源区（14）的至少第一部分和垂直有源区（16）的至少第一部分上形成栅极电介质（26）。 该方法还包括在栅极电介质（26）上形成栅电极（28）。 该方法还包括在水平有源区的至少第二部分和垂直有源区（16）的至少第二部分之上形成源极区（30）和漏极区（32）。

公开(公告)号：WO2005045892A2

公开(公告)日：2005-05-19

申请号：PCT/US2004035349

申请日：2004-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  MORA RODE R ,  NGUYEN BICH-YEN ,  STEPHENS TAB A ,  VANDOOREN ANNE M

Inventor： MATHEW LEO ,  MORA RODE R ,  NGUYEN BICH-YEN ,  STEPHENS TAB A ,  VANDOOREN ANNE M

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L

CPC classification number: H01L29/785 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/66818

Abstract: A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.

Abstract translation: 半导体制造工艺包括形成覆盖衬底的硅片。 栅极电介质形成在鳍片的主面上。 在鳍片的至少两个面上形成栅电极。 然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。 此后，在主翅片面上形成硅化物。 在一个实施例中，栅电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻 产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。

公开(公告)号：WO2009046114A3

公开(公告)日：2009-05-22

申请号：PCT/US2008078460

申请日：2008-10-01

Applicant: UNIV FLORIDA ,  FOSSUM JERRY G ,  MATHEW LEO ,  SADD MICHAEL ,  TRIVEDI VISHAL P

Inventor： FOSSUM JERRY G ,  MATHEW LEO ,  SADD MICHAEL ,  TRIVEDI VISHAL P

IPC: H01L21/8242

CPC classification number: H01L27/108 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L27/10826 ,  H01L29/7841 ,  H01L29/785

Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded- DRAM applications. Further embodiments pertain to a floating-body/ gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.

Abstract translation: 实施例涉及用于嵌入式DRAM应用的双晶体管（2T）浮体单元（FBC）。 除了更好的信号裕量，更长的数据保持时间和更高的存储器密度之外，进一步的实施例涉及浮体/栅单元（FBGC），其减小功耗。

公开(公告)号：WO2007120296A3

公开(公告)日：2008-12-31

申请号：PCT/US2006061312

申请日：2006-11-29

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  KHAZHINSKY MICHAEL G

Inventor： MATHEW LEO ,  KHAZHINSKY MICHAEL G

IPC: H01L23/58

CPC classification number: H01L27/0811 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/7391 ,  H01L29/785

Abstract: An electronic device (10) can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member (101) spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member (102), spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated (32, 22) from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

Abstract translation: 电子设备（10）可以包括门控二极管，其中门控二极管包括包括结的结二极管结构。 与结点隔开并相邻的第一导电构件（101）可以连接到第一信号线。 与结点间隔开并与其相邻的第二导电构件（102）可以电连接到第二信号线并与第一导电构件电绝缘（32,22）。 结二极管结构可以包括p-n或p-i-n结。 还描述了用于形成电子设备的过程。

公开(公告)号：WO2007120292A3

公开(公告)日：2008-10-16

申请号：PCT/US2006061278

申请日：2006-11-28

Applicant: FREESCALE SEMICONDUCTOR INC ,  BURNETT JAMES D ,  MATHEW LEO ,  MIN BYOUNG W

Inventor： BURNETT JAMES D ,  MATHEW LEO ,  MIN BYOUNG W

IPC: H01L29/00

CPC classification number: H01L27/1108 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit (10) includes a logic circuit and a memory cell (21). The logic circuit includes a P-channel transistor (18), and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).

Abstract translation: 集成电路（10）包括逻辑电路和存储单元（21）。 逻辑电路包括P沟道晶体管（18），并且存储单元包括P沟道晶体管。 逻辑电路的P沟道晶体管包括沟道区。 沟道区具有位于具有（110）表面取向的半导体结构的侧壁的部分。 位于沿着侧壁的通道区域的部分具有第一垂直尺寸，其大于沿着具有表面的半导体结构的侧壁的存储单元的P沟道晶体管的沟道区的任何部分的垂直尺寸 （110）的方向。

公开(公告)号：WO2007098305A3

公开(公告)日：2008-03-13

申请号：PCT/US2007060843

申请日：2007-01-22

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  GE LIXIN ,  VEERARAGHAVAN SURYA

Inventor： MATHEW LEO ,  GE LIXIN ,  VEERARAGHAVAN SURYA

IPC: H01L27/12

CPC classification number: H01L29/78615 ,  H01L29/785

Abstract: A method for making a semiconductor device includes patterning a semiconductor layer (14), overlying an insulator layer (12), to create a first active region (28) and a second active region (30), wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure (26) over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

Abstract translation: 制造半导体器件的方法包括图案化覆盖绝缘体层（12）的半导体层（14），以形成第一有源区（28）和第二有源区（30），其中第一有源区为 与第二有源区不同的高度，并且其中第一有源区的至少一部分具有第一导电类型，并且第二有源区的至少一部分具有与至少一个沟道中的第一导电类型不同的第二导电类型 半导体器件的区域。 该方法还包括在第一有源区域和第二有源区域的至少一部分上形成栅极结构（26）。 该方法还包括去除半导体器件的一侧上的第二有源区的一部分。