TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS
    1.
    发明申请
    TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS 审中-公开
    用于基于TSV的3D堆叠ICS的测试访问架构

    公开(公告)号:WO2011117418A1

    公开(公告)日:2011-09-29

    申请号:PCT/EP2011/054722

    申请日:2011-03-28

    Abstract: A test access architecture is presented for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external l/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.

    Abstract translation: 为3D-SIC提供了测试访问体系结构,可以进行预绑定模块测试和后绑定堆栈测试。 测试访问架构基于模块化测试方法,其中各种模具,其嵌入式IP内核,基于芯片间TSV的互连和外部I / O可以作为单独的单元进行测试,从而优化3D -SIC测试流程。 该架构建立并重用现有的核心,管芯和产品级测试(DfT)硬件设计。 通过称为包装单元的测试结构将测试访问提供给单个管芯堆叠。

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