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公开(公告)号：WO2016083620A1
公开(公告)日：2016-06-02
申请号：PCT/EP2015/078089
申请日：2015-11-30
Applicant: IMEC TAIWAN CO. , IMEC VZW
Inventor： HSIAO, Ching-Chun , CHANG, Ting-Ting , LIAO, Chao Kang
IPC: G03H1/08
CPC classification number: G03H1/0866 , G03H2001/0447 , G03H2001/0883 , G06T7/11 , G06T7/13 , G06T7/136 , G06T7/187
Abstract: The present invention discloses an autofocus method for determining an optimal focal plane. The method comprises reconstructing (201) a holographic image and performing (203) a first edge detection at least two reconstructed depths, based on the real part of the reconstructed image, and performing a second edge detection at these reconstructed depths, based on the imaginary part of the reconstructed image. The method further comprises obtaining (204) a first and second measure of clearness for each depth based on a statistical dispersion with respect to respectively the first and the second edge detection. The method also comprise determining (205) the focal plane for the at least one object based on a comparison of a scalar measure of clearness for the at least two depths, in which this scalar measure is based on the first and the second measure of clearness.
Abstract translation: 本发明公开了一种用于确定最佳焦平面的自动对焦方法。 该方法包括重建（201）全息图像，并且基于重构图像的实部执行（203）至少两个重构深度的第一边缘检测，并且基于该假想图像在这些重建深度处执行第二边缘检测 部分重建图像。 该方法还包括基于相对于第一和第二边缘检测的统计色散来获得（204）针对每个深度的第一和第二清晰度的度量。 该方法还包括基于对至少两个深度的清晰度的标量测量值的比较来确定（205）所述至少一个对象的焦平面，其中该标量度量基于第一和第二清晰度量度 。
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公开(公告)号：WO2011117418A1
公开(公告)日：2011-09-29
申请号：PCT/EP2011/054722
申请日：2011-03-28
Applicant: IMEC , STICHTING IMEC NEDERLAND , MARINISSEN, Erik Jan , VERBREE, Jacobus , KONIJNENBURG, Mario , CHI, Chun-Chuan
Inventor： MARINISSEN, Erik Jan , VERBREE, Jacobus , KONIJNENBURG, Mario , CHI, Chun-Chuan
IPC: G01R31/3185
CPC classification number: G01R31/318508 , G01R31/31717 , G01R31/3177 , G01R31/318511 , G01R31/318513 , G01R31/318572
Abstract: A test access architecture is presented for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external l/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.
Abstract translation: 为3D-SIC提供了测试访问体系结构，可以进行预绑定模块测试和后绑定堆栈测试。 测试访问架构基于模块化测试方法，其中各种模具，其嵌入式IP内核，基于芯片间TSV的互连和外部I / O可以作为单独的单元进行测试，从而优化3D -SIC测试流程。 该架构建立并重用现有的核心，管芯和产品级测试（DfT）硬件设计。 通过称为包装单元的测试结构将测试访问提供给单个管芯堆叠。
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公开(公告)号：WO2022064032A1
公开(公告)日：2022-03-31
申请号：PCT/EP2021/076478
申请日：2021-09-27
Inventor： SIGNORELLO, Giorgio , FURXHI, Orges , VAN CAMPENHOUT, Joris , VASILIEV, Anton , ROUSSEAUX, Olivier
IPC: G01N21/3504 , G01N21/27 , G01N21/03
Abstract: The present disclosure relates to an optical alignment compensation system for a gas detection system, in particular, to an integrated alignment compensation system for an open-path gas sensing system. The optical alignment compensation system of the disclosure is able to compensate for unwanted drifts of a retroreflector. The optical alignment system comprises an array of transceiver pairs, wherein each transceiver pair is configured to transmit and receive light with an optical spectrum in an absorption region of a gas to be detected. Further, it comprises a retroreflector arranged at a nominal position and configured to reflect the light. Further, it comprises an optical element arranged and configured to direct the light from at least one of the transceiver pairs along an optical path through the gas to the retroreflector, to receive the light reflected by the retroreflector along the optical path, and to direct the reflected light to the respective transceiver pair. Further, it comprises a control unit configured to select one of the transceiver pairs for transmitting and receiving the light, wherein the control unit is configured to select the transceiver pair that receives the reflected light with the highest signal response.
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公开(公告)号：WO2020234278A1
公开(公告)日：2020-11-26
申请号：PCT/EP2020/063919
申请日：2020-05-19
Applicant: IMEC VZW , STICHTING IMEC NEDERLAND , UNIVERSITEIT GENT
Inventor： VAN LIEMPD, Chris , VASQUEZ QUINTERO, Andres Felipe , DE SMET, Herbert
Abstract: A smart contact lens (400) for detecting a ratiometric change in an incident light (126) intensity is provided, including one or more, preferably concentric, rings (410-1, 410-2, …, 410-N) of a liquid crystal display, LCD, type, each ring being operable between a state having a lower attenuation of light and a state having a higher attenuation of light; a circuit (420, 100, 101) for detecting a ratiometric change in an incident light intensity; and a controller (430) configured to operate the one or more rings based on an intensity of an incident light and to, as a response to the circuit (420, 100, 10 101) detecting a ratiometric change in the intensity of the incident light from a higher intensity state to a lower intensity state indicating that at least a beginning of a blinking of an eye of a user has occurred, initiate a re-polarization of the one or more rings. A method of operating the smart contact lens and various uses of the circuit are also provided.
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公开(公告)号：WO2012119988A1
公开(公告)日：2012-09-13
申请号：PCT/EP2012/053757
申请日：2012-03-05
Applicant: IMEC , Stichting IMEC Nederland , Katholieke Universiteit Leuven , SHARMA, Vibhu , COSEMANS, Stefan , DEHAENE, Wim , CATTHOOR, Francky , ASHOUEI, Maryam , HUISKEN, Jos
Inventor： SHARMA, Vibhu , COSEMANS, Stefan , DEHAENE, Wim , CATTHOOR, Francky , ASHOUEI, Maryam , HUISKEN, Jos
IPC: G11C11/419
CPC classification number: G11C11/419 , G11C7/18 , G11C11/412
Abstract: Memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.
Abstract translation: 存储器件具有互补的全局和局部位线，所述互补局部位线可通过本地写入接收器连接到互补的全局位线，所述本地写入接收器经配置以在互补的局部位线上从 在互补的全局位线上降低电压摆幅。 本地写接收器包括用于将本地连接到全局位线的连接机构和直接连接到互补局部位线的一对交叉耦合的反相器，用于将互补局部位上的降低的电压摆幅转换为全电压摆幅 线。
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Patent Agency Ranking
公开(公告)号：WO2022130127A1
公开(公告)日：2022-06-23
申请号：PCT/IB2021/061462
申请日：2021-12-08
Applicant: DEPUY SYNTHES PRODUCTS, INC. , STICHTING IMEC NEDERLAND , IMEC VZW
Inventor： MIKHAIL, George , VU, Binh , WALSER, Jochen , DLUGOS, Dan , FICHMAN, Mark , LEE, Seulki , SHAHRIARI, Navid , SHEIKHI, Erfan , OP DE BEECK, Maria
Abstract: An implantable device includes a substrate and protective cover that cooperate to define an enclosed sensor volume. A sealed enclosure is provided within the sensor volume, with an electronic component assembly (ECA) being located within the sealed enclosure. A flexible circuit board assembly (FCBA) is electrically coupled with the ECA through a wall of the sealed enclosure. At least one transducer is provided on the FCBA in contact with the substrate, and the FCBA is held apart from the enclosure via a polymeric spacer provided therebetween. An inert polymer fill is provided within the sensor volume external to the enclosure.
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公开(公告)号：WO2011003803A1
公开(公告)日：2011-01-13
申请号：PCT/EP2010/059362
申请日：2010-07-01
Applicant: IMEC , STICHTING IMEC NEDERLAND , KATHOLIEKE UNIVERSITEIT LEUVEN , STERKEN, Tom , ALTENA, Geert , GOEDBLOED, Martijn , PUERS, Robert
Inventor： STERKEN, Tom , ALTENA, Geert , GOEDBLOED, Martijn , PUERS, Robert
Abstract: A method for fabricating an out-of-plane variable overlap MEMS capacitor comprises: providing a substrate (40) comprising a first layer (41), a second layer (42), and a third layer (43) stacked on top of one another; and etching a plurality of first trenches (70) through the third layer (43), through the second layer (42), and into the first layer (41) using a single etching mask. Etching the plurality of first trenches (70) defines a plurality of first fingers (51) in the third layer (43) and a plurality of second fingers (52) in the first layer (41). By using a single mask, the process is self-aligned. The method further comprises removing the second layer (42) in a first region where the plurality of first trenches (70) are provided, thereby forming a spacing or gap between the plurality of first fingers (51) and the plurality of second fingers (52).
Abstract translation: 一种用于制造面外可变重叠MEMS电容器的方法包括：提供包括第一层（41），第二层（42）和堆叠在彼此顶部的第三层（43）的衬底（40） ; 以及通过所述第三层（43）通过所述第二层（42）蚀刻多个第一沟槽（70），并使用单个蚀刻掩模蚀刻到所述第一层（41）中。 蚀刻多个第一沟槽（70）在第三层（43）中限定多个第一指状物（51）和第一层（41）中的多个第二指状物（52）。 通过使用单个掩模，该过程是自对准的。 该方法还包括在设置有多个第一沟槽（70）的第一区域中移除第二层（42），从而在多个第一指状物（51）和多个第二指状物（52）之间形成间隔或间隙 ）。
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公开(公告)号：WO2023030653A1
公开(公告)日：2023-03-09
申请号：PCT/EP2021/074400
申请日：2021-09-03
Applicant: IMEC VZW , HUAWEI TECHNOLOGIES CO., LTD.
Inventor： RAWAT, Amita , WU, Hao , HELLINGS, Geert , BHUWALKA, Krishna Kumar
IPC: H01L21/8238 , H01L27/092 , H01L29/775
Abstract: A nanostructure according to the invention comprises a pair of nanosheet or nanowire transistors (1,1') configured to conduct charge by carriers of opposite polarity (such as n and p type carriers), wherein one of the two transistors is provided with inner spacers (10) and the other is not provided with inner spacers. The inventors found that depending on the type of charge carrier, the omission of the inner spacers may offer an unexpected improvement in the admittance of the device that outweighs the negative impact of the inner spacer omission. This is the case for example in a Si-channel PMOS nanosheet transistor (1'), whereas in a Si channel NMOS nanosheet transistor (1), the omission of the inner spacers has a negative effect on the parasitic capacitance that outweighs any benefits of the inner spacer omission. A preferred embodiment of the invention therefore includes complementary NMOS and PMOS silicon transistors (1,1'), wherein the NMOS is provided with inner spacers (10), whereas the PMOS is not provided with inner spacers.
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公开(公告)号：WO2023017048A1
公开(公告)日：2023-02-16
申请号：PCT/EP2022/072376
申请日：2022-08-09
Applicant: UNIVERSITEIT GENT , IMEC VZW
Inventor： BOGAERTS, Wim , VAN ISEGHEM, Lukas
Abstract: An optical antenna comprising a waveguide structure comprising a waveguide core and a waveguide fin intersecting substantially under a right angle, wherein: − a height of the waveguide fin (120) is larger than a height of the waveguide core (110); and − the width of the waveguide core (110) is equal to or larger than twice a height of the waveguide core (110); and − the height of the waveguide fin (120) is equal to or larger than twice a width of the waveguide fin (120); and wherein the waveguide fin is off-centered with respect to the waveguide core at an offset, thereby forming an optical antenna configured to leak radiation in a radiation direction. Further example embodiments relate to an optical phased antenna array comprising a plurality of such optical antennas arranged in an array configuration.
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公开(公告)号：WO2023001715A1
公开(公告)日：2023-01-26
申请号：PCT/EP2022/069928
申请日：2022-07-15
Applicant: UNIVERSITEIT GENT , IMEC VZW
Inventor： NIU, Shengpu , LAMBRECHT, Joris , VERPLAETSE, Michiel , XIN, Yin
Abstract: The present disclosure relates to a sampling circuit for sampling an analog input signal comprising: a capacitive means, a reset switch, and a sampling switch; the reset switch and the sampling switch being connected to a signal generator circuit configured to provide periodic reset and sampling control signals to the respective switches for controlling their operation; wherein the respective periodic reset and sampling control signals have equal duty factors and signal periods, and a phase delay with respect to one another being less than the signals' duty factor, thereby forming an overlap period during which the reset switch and the sampling switch remain closed.
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