公开(公告)号：WO2005088890A1

公开(公告)日：2005-09-22

申请号：PCT/RU2005/000118

申请日：2005-03-11

Applicant: ABROSIMOV, Igor Anatolievich

Inventor： ABROSIMOV, Igor Anatolievich ,  DEAS, Alexander, Roger ,  FAULDS, Gordon, John ,  KLOTCHKOV, Ilya Valerievich

IPC: H04L7/02

CPC classification number: H04L7/0054

Abstract: The present invention relates to the reduction of timing uncertainty in high speed communications channel or interface and to a receiver and method using the same. The receiver according to the invention uses an over sampled data stream to detect bits, analyses the sampled stream of bits, determines valid samples and then expand them into a minimal eye required for accurate and reliable data reading. The present invention includes capability to track an eye across sample blocks, correcting for jitter.

Abstract translation: 本发明涉及降低高速通信信道或接口中的定时不确定性以及使用该定时不确定性的方法。 根据本发明的接收机使用过采样数据流来检测比特，分析采样的比特流，确定有效样本，然后将它们扩展到精确和可靠的数据读取所需的最小的眼睛。 本发明包括在样本块之间跟踪眼睛的能力，以纠正抖动。

公开(公告)号：WO2003100974A3

公开(公告)日：2003-12-04

申请号：PCT/RU2003/000242

申请日：2003-05-28

Applicant: ABROSIMOV, Igor Anatolievich

Inventor： ABROSIMOV, Igor Anatolievich

IPC: H03K19/017

Abstract: The present invention relates to a pull-up structure with variable strength, which combines a resistor network with N type MOS transistors. According to the invention, the pull up structure comprises a n-channel type MOSFET (51) with a resistor (52) in parallel. Alternatively, a resistor (54) is connected between the terminal of the pull up and a voltage supply. This allows the pull up to be varied to compensate for process and temperature variations around a predefined pull-up strength, and at the same time provides low parasitic capacitance and a good dynamic response of the pull-up structure.

公开(公告)号：WO2003100974A2

公开(公告)日：2003-12-04

申请号：PCT/RU2003/000242

申请日：2003-05-28

Applicant: ABROSIMOV, Igor Anatolievich

Inventor： ABROSIMOV, Igor Anatolievich

IPC: H03K

CPC classification number: H03K19/01721

Abstract: The present invention relates to a pull-up structure with variable strength, which combines a resistor network with N type MOS transistors. According to the invention, the pull up structure comprises a n-channel type MOSFET with a resistor in parallel. Alternatively, a resistor is connected between the terminal of the pull up and a voltage supply. This allows the pull up to be varied to compensate for process and temperature variations around a predefined pull-up strength, and at the same time provides low parasitic capacitance and a good dynamic response of the pull-up structure.

Abstract translation: 本发明涉及一种具有可变强度的上拉结构，其结合了电阻网络与N型MOS晶体管。 根据本发明，上拉结构包括具有并联电阻器的n沟道型MOSFET。 或者，电阻器连接在上拉端子和电源之间。 这允许上拉变化以补偿围绕预定义的上拉强度的工艺和温度变化，并且同时提供较低的寄生电容和上拉结构的良好的动态响应。

公开(公告)号：WO2003100973A2

公开(公告)日：2003-12-04

申请号：PCT/RU2003/000241

申请日：2003-05-28

Applicant: ABROSIMOV, Igor Anatolievich

Inventor： ABROSIMOV, Igor Anatolievich

IPC: H03K

CPC classification number: H03K3/011 ,  H03K3/0322

Abstract: A reference voltage generator employs a ring oscillator having a plurality of logic stages and a phase/frequency detector, for generating a first feedback signal on the basis of a phase/frequency difference between the phase/frequency of a reference clock and the phase/frequency of the ring oscillator; and to generate a second feedback signal on the basis of a voltage swing of the oscillator circuit; both feedback signals to be applied to said plurality of logic stages of the ring oscillator; whereby a constant delay is created through each logic stage of the logic device. In another aspects of the invention, a method of generating a reference voltage for a logic device by using the reference voltage generator as above and a logic device with a controlled propagation delay of each of the logic stages are provided.

Abstract translation: 参考电压发生器采用具有多个逻辑级的环形振荡器和相位/频率检测器，用于基于参考时钟的相位/频率与相位/频率之间的相位/频率差产生第一反馈信号 的环形振荡器; 并且基于所述振荡器电路的电压摆幅来产生第二反馈信号; 两个反馈信号将被施加到环形振荡器的所述多个逻辑级; 从而通过逻辑器件的每个逻辑级产生恒定的延迟。 在本发明的另一方面中，提供了通过使用上述参考电压发生器产生用于逻辑器件的参考电压的方法和具有每个逻辑级的受控传播延迟的逻辑器件。

公开(公告)号：WO2006025768A2

公开(公告)日：2006-03-09

申请号：PCT/RU2005/000438

申请日：2005-08-19

Applicant: ABROSIMOV, Igor Anatolievich

Inventor： ABROSIMOV, Igor Anatolievich ,  DEAS, Alexander, Roger ,  COYNE, David

CPC classification number: H04L25/14

Abstract: The invention relates to a communications receiver with reduced latency and method that offsets the receiver framing alignment to minimize the decode latency for return data. The receiver comprises transceiver cells for deserialising data received in frames from a host computer into a parallel output data word of width equal to the number of bits in the frame; and a memory interface controller for decoding the parallel frame data from the transceiver cells and generating control signals and data signals to a memory device. The phase of the deserialised output data is adjusted to offset the parallel output data word to the frame control clock, so that the parallel output data word is aligned to the frame control clock such that the output data becomes valid when the command field has been deserialised. This provides improved clocking alignment for any downstream components operating on the data contained within the frame structure.

Abstract translation: 本发明涉及具有减小的等待时间和方法的通信接收机，其抵消接收机成帧对准以最小化返回数据的解码延迟。 接收机包括用于将从主计算机帧中接收的数据反序列化为宽度等于帧中的位数的并行输出数据字的收发器单元; 以及存储器接口控制器，用于对来自收发器单元的并行帧数据进行解码，并向存储器件产生控制信号和数据信号。 调整反序列化输出数据的相位以将并行输出数据字偏移到帧控制时钟，使得并行输出数据字与帧控制时钟对准，使得当命令字段被反序列化时，输出数据变为有效 。 这为在框架结构中包含的数据上运行的任何下游组件提供了改进的时钟对准。

公开(公告)号：WO2005057805A1

公开(公告)日：2005-06-23

申请号：PCT/RU2004/000490

申请日：2004-12-06

Applicant: ABROSIMOV, Igor Anatolievich

Inventor： ABROSIMOV, Igor Anatolievich ,  DEAS, Alexander, Roger ,  COYNE, David

IPC: H04B3/23

CPC classification number: H04B3/23 ,  H04B1/58 ,  H04B3/03 ,  H04L25/085

Abstract: Bidirectional differential point to point simultaneous high speed signalling is provided between integrated circuits with highly effective echo canceling. Each integrated circuit comprises a transmitter for transmitting a first signal to another integrated circuit and a receiver for receiving a second signal from the other integrated circuit. The transmitter has an output buffer; a receiver has a receiver buffer and is co-located on the same integrated circuit; and a signal processing circuit is coupled between the input of the transmitter buffer and the output of the receiver buffer. To increase the quality of receiving the second signal, a third signal adjusted in phase and amplitude is coupled at the output of the receive buffer, so that the echoing of the first signal is canceled. Preferably, the rise time of the third signal is also adjusted.

Abstract translation: 在具有高效回波消除的集成电路之间提供双向差分点对点同时高速信号。 每个集成电路包括用于将第一信号发送到另一集成电路的发射机和用于从另一集成电路接收第二信号的接收机。 发射机有一个输出缓冲器; 接收器具有接收器缓冲器并且位于同一集成电路上; 并且信号处理电路耦合在发送器缓冲器的输入端和接收器缓冲器的输出之间。 为了增加接收第二信号的质量，在接收缓冲器的输出处耦合相位和振幅调节的第三信号，从而消除第一信号的回波。 优选地，也调整第三信号的上升时间。

公开(公告)号：WO2003100973A3

公开(公告)日：2003-12-04

申请号：PCT/RU2003/000241

申请日：2003-05-28

Applicant: ABROSIMOV, Igor Anatolievich

Inventor： ABROSIMOV, Igor Anatolievich

IPC: H03K3/354

Abstract: A reference voltage generator employs a ring oscillator having a plurality of logic stages and a phase/frequency detector, for generating a first feedback signal on the basis of a phase/frequency difference between the phase/frequency of a reference clock and the phase/frequency of the ring oscillator; and to generate a second feedback signal on the basis of a voltage swing of the oscillator circuit; both feedback signals to be applied to said plurality of logic stages of the ring oscillator; whereby a constant delay is created through each logic stage of the logic device. In another aspects of the invention, a method of generating a reference voltage for a logic device by using the reference voltage generator as above and a logic device with a controlled propagation delay of each of the logic stages are provided.

公开(公告)号：WO2006006893A1

公开(公告)日：2006-01-19

申请号：PCT/RU2005/000371

申请日：2005-07-04

Applicant: ABROSIMOV, Igor Anatolievich

Inventor： ABROSIMOV, Igor Anatolievich ,  DEAS, Alexander, Roger ,  COYNE, David

IPC: H04L7/033

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/095 ,  H04L7/033

Abstract: A receiver containing a clock and data recovery circuit operating at a quarter-rate clock frequency is provided for high-speed signalling between integrated circuits. Each integrated circuit comprises a receiver for receiving a first signal from the other integrated circuit. The receiver has a clock and data recovery phase locked loop.

Abstract translation: 包含以四分之一时钟频率工作的时钟和数据恢复电路的接收器被提供用于集成电路之间的高速信令。 每个集成电路包括用于从另一集成电路接收第一信号的接收器。 接收机具有时钟和数据恢复锁相环。

公开(公告)号：WO2003065670A1

公开(公告)日：2003-08-07

申请号：PCT/IB2003/000356

申请日：2003-01-29

Applicant: ABROSIMOV, Igor Anatolievich

Inventor： ABROSIMOV, Igor Anatolievich ,  DEAS, Alexander, Roger ,  FAULDS, Gordon, John

IPC: H04L25/49

CPC classification number: H04L25/4908

Abstract: The present invention relates to the reduction of artifacts introduced by sending data at a higher rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Abstract translation: 本发明涉及通过以比通信信道的带宽更高的速率发送数据而引入的伪像的减少，诸如作为前面数据的函数在接收机处的数据中引入的电压和电流偏移。

公开(公告)号：WO2002078228A2

公开(公告)日：2002-10-03

申请号：PCT/RU2002/000120

申请日：2002-03-26

Applicant: ABROSIMOV, Igor Anatolievich

Inventor： ABROSIMOV, Igor Anatolievich ,  DEAS, Alexander, Roger

IPC: H04J3/00

CPC classification number: H04L7/0054 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0045 ,  H04L7/033 ,  H04L25/14

Abstract: The present invention relates to the reduction of timing uncertainty in high speed communications channel or interface and to a receiver and method using the same. The receiver according to the invention comprises a plurality of samplers for latching data. The invention provides improvements to the Bit Error rate versus channel and inherent register noise, as a result of employment of the characteristic of phase noise within the receiving registers to measure the characteristics of the channel and to compensate for variations in the channel by altering the timing characteristics of the signal.

Abstract translation: 本发明涉及在高速通信信道或接口中不确定地减少时序。 根据本发明的接收机包括用于锁存数据的多个采样器。 本发明通过使用接收寄存器内的相位噪声的特性来测量信道的特性并且通过改变定时来补偿信道的变化，从而提供了比特误码率对信道和固有寄存器噪声的改进 信号的特点。