-
公开(公告)号：WO2022104082A1
公开(公告)日：2022-05-19
申请号：PCT/US2021/059172
申请日：2021-11-12
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： ACHARYA, Anirudh, R. , WU, Ruijin , YEO, Young, In
IPC: G06T1/20 , G06F9/50 , G06F9/48 , G06F1/3203
Abstract: Systems and methods related to priority-based and performance-based selection of a render mode, such as a two-level binning mode, in which to execute workloads with a graphics processing unit (GPU) [102] of a system [100] are provided. A user mode driver (UMD) [110] or kernel mode driver (KMD) [112] executed at a central processing unit (CPU) [104] configures low and medium priority workloads to be executed in a two-level binning mode and selects a binning mode for high priority workloads based on whether performance heuristics indicate that one or more binning conditions or override conditions have been met. High priority workloads are maintained in a high priority queue, while low and medium priority workloads are maintained in a low/medium priority queue, such that execution of low and medium priority workloads at the GPU can be preempted in favor of executing high priority workloads.
-
公开(公告)号：WO2021262370A1
公开(公告)日：2021-12-30
申请号：PCT/US2021/033943
申请日：2021-05-24
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： ACHRENIUS, Jan H. , KALLIO, Kiia , KANGASLUOMA, Miikka , WU, Ruijin , ACHARYA, Anirudh R.
IPC: G06T1/20 , G06T15/00 , G06T11/40 , G06T15/005 , G06T17/10
Abstract: Some implementations provide systems, devices, and methods for rendering a plurality of primitives of a frame, the plurality of primitives being divided into a plurality of batches of primitives and the frame being divided into a plurality of bins. For at least one batch of the plurality of batches the rendering includes, for each of the plurality of bins, rendering primitives of a first sub-batch rasterizing to that bin, and for each of the plurality of bins, rendering primitives of a second sub-batch rasterizing to that bin.
-
公开(公告)号：WO2022146928A1
公开(公告)日：2022-07-07
申请号：PCT/US2021/065230
申请日：2021-12-27
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： ACHARYA, Anirudh R. , WU, Ruijin
Abstract: Systems (100) and methods (300) for distributed rendering using two-level binning inlcude processing primitives (208) of a frame (202) to be rendered at a first graphics processing unit (GPU) chiplet (106-1) in a set of GPU chiplets (106) to generate visibility information (408) of primitives for each coarse bin (204, 510, 512, 514, 516, 518) and providing the visibility information (408) to the other GPU chiplets in the set of GPU chiplets (106). Each coarse bin (204, 510, 512, 514, 516, 518) is assigned to one of the GPU chiplets of the set of GPU chiplets (106) and rendered at the assigned GPU chiplet (106) based on the corresponding visibility information (408).
-
公开(公告)号：WO2021061532A1
公开(公告)日：2021-04-01
申请号：PCT/US2020/051647
申请日：2020-09-18
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： WU, Ruijin , SALEH, Skyler Jonathon , GOEL, Vineet
Abstract: A technique for operating a processor that includes multiple cores is provided. The technique includes determining a number of active applications, selecting a processor configuration for the processor based on the number of active applications, configuring the processor according to the selected processor configuration, and executing the active applications with the configured processor.
-
公开(公告)号：WO2019040630A1
公开(公告)日：2019-02-28
申请号：PCT/US2018/047539
申请日：2018-08-22
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： KAZAKOV, Maxim V. , SALEH, Skyler J. , WU, Ruijin , BHANDARE, Sagar Shankar
Abstract: A pipeline is configured to access a memory that stores a texture block and metadata that encodes compression parameters of the texture block and a residency status of the texture block. A processor requests access to the metadata in conjunction with requesting data in the texture block to perform a shading operation. The pipeline selectively returns the data in the texture block to the processor depending on whether the metadata indicates that the texture block is resident in the memory. A cache can also be included to store a copy of the metadata that encodes the compression parameters of the texture block. The residency status and the metadata stored in the cache can be modified in response to requests to access the metadata stored in the cache.
-
Patent Agency Ranking
公开(公告)号：WO2022211966A1
公开(公告)日：2022-10-06
申请号：PCT/US2022/018795
申请日：2022-03-03
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： TUOMI, Mika , WU, Ruijin , ACHARYA, Anirudh R.
Abstract: A method and apparatus of tile rendering of an image for a display in a computer system includes receiving the image in a graphics pipeline of the computer system, the image comprising one or more three dimensional (3D) objects. The image is divided into one or more tiles. A depth test is performed on the one or more tiles, and based upon the depth test, visibility information of the one or more tiles is binned.
-
公开(公告)号：WO2022031957A1
公开(公告)日：2022-02-10
申请号：PCT/US2021/044720
申请日：2021-08-05
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： ACHARYA, Anirudh , WU, Ruijin , RUGGIERI, Paul
IPC: G06T1/20 , G06T1/60 , G06F9/50 , G06F1/3212 , G06F9/4893
Abstract: Systems and methods related to run-time selection of a render mode in which to execute command buffers with a graphics processing unit (GPU) of a device based on performance data corresponding to the device are provided. A user mode driver (UMD) or kernel mode driver (KMD) executed at a central processing unit (CPU) selects a binning mode based on whether performance data that includes sensor data or performance counter data indicates that an associated binning condition or override condition has been met. The UMD or the KMD causes pending command buffers to be patched to execute in the selected binning mode based on whether the binning mode is enabled or disabled.
-
公开(公告)号：WO2021183545A1
公开(公告)日：2021-09-16
申请号：PCT/US2021/021550
申请日：2021-03-09
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： ACHARYA, Anirudh R. , WU, Ruijin , YEO, Young In , TUOMI, Mika , KALLIO, Kiia
Abstract: A processor dynamically selects a render mode for each render pass of a frame based on the characteristics of the render pass. A software driver of the processor receives graphics operations from an application executing at the processor and converts the graphics operations into a command stream that is provided to the graphics pipeline. As the driver converts the graphics operations into the command stream, the driver analyzes each render pass of the frame to determine characteristics of the render passes, and selects a render mode for each render pass based on the characteristics of the render pass.
-
公开(公告)号：WO2023004028A1
公开(公告)日：2023-01-26
申请号：PCT/US2022/037848
申请日：2022-07-21
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： ACHARYA, Anirudh , GODEY, Sreekanth , WU, Ruijin
IPC: G06F9/50 , G06F9/455 , G06F9/5038 , G06F9/5044 , G06F9/505 , G06F9/5077
Abstract: A processing unit [100] is configured differently based on an identified workload [200, 225], and each configuration of the processing unit is exposed to software (e.g., to a device driver [103]) as a different virtual processing unit [111. 112]. Using these techniques, a processing system is able to provide different configurations of the processing unit to support different types of workloads, thereby conserving system resources. Further, by exposing the different configurations as different virtual processing units, the processing system is able to use existing device drivers or other system infrastructure to implement the different processing unit configurations.
-
公开(公告)号：WO2022203833A1
公开(公告)日：2022-09-29
申请号：PCT/US2022/018794
申请日：2022-03-03
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： WU, Ruijin , TUOMI, Mika , PESSI, Paavo Sampo Ilmari , ACHARYA, Anirudh R.
Abstract: A method of tiled rendering is provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles and interleaving execution of same subpasses of multiple tiles of the frame. Interleaving execution of same subpasses of multiple tiles comprises executing a previously ordered first subpass of a second tile between execution of the previously ordered first subpass of a first tile and execution of a subsequently ordered second subpass of the first tile. The interleaving is performed, for example, by executing the plurality of subpasses in an order different from the order in which the commands to execute the plurality of subpasses are stored and issued. Alternatively, interleaving is performed by executing one or more subpasses as skip operations such that the plurality of subpasses are executed in the same order.
-
-
-
-
-
-
-
-
-
Search Results
18
records
(took 0.031 seconds)
