公开(公告)号：WO2022033793A1

公开(公告)日：2022-02-17

申请号：PCT/EP2021/069613

申请日：2021-07-14

Applicant: ASML NETHERLANDS B.V.

Inventor： COLLIGNON, Tijmen, Pieter ,  SMAL, Pavel ,  TABERY, Cyrus, Emil ,  DOS SANTOS GUZELLA, Thiago ,  BASTANI, Vahid

IPC: G03F7/20 ,  G03F9/00

Abstract: Methods and associated apparatus for identifying contamination in a semiconductor fab are disclosed. The methods comprise determining contamination map data for a plurality of semiconductor wafers clamped to a wafer table after being processed in the semiconductor fab. Combined contamination map data is determined based, at least in part, on a combination of the contamination map data of the plurality of semiconductor wafers. The combined contamination map data is combined to reference data. The reference data comprises one or more values for the combined contamination map data that are indicative of contamination in one or more tools in the semiconductor fab.

公开(公告)号：WO2020108861A1

公开(公告)日：2020-06-04

申请号：PCT/EP2019/078529

申请日：2019-10-21

Applicant: ASML NETHERLANDS B.V.

Inventor： SMAL, Pavel ,  SOCHAL, Inez, Marlena ,  SARMA, Gautam

IPC: G03F7/20 ,  G03F9/00

Abstract: A method for determining a layout of mark positions across a patterning device or substrate, the method comprising: a) obtaining (502) a model configured to model data associated with measurements performed on the patterning device or substrate at one or more mark positions; b) obtaining (504) an initial mark layout (506) comprising initial mark positions; c) reducing (508) the initial mark layout by removal of one or more mark positions to obtain a plurality of reduced mark layouts (510), each reduced mark layout obtained by removal of a different mark position from the initial mark layout; d) determining (512) a model uncertainty metric associated with usage of the model for each reduced mark layout out of said plurality of reduced mark layouts; and e) selecting (514) one or more reduced mark layouts (516) based on its associated model uncertainty metric.