公开(公告)号：WO1993018586A1

公开(公告)日：1993-09-16

申请号：PCT/US1993000469

申请日：1993-01-19

Applicant: ATMEL CORPORATION

Inventor： ATMEL CORPORATION ,  GONGWER, Geoffrey, S. ,  TAM, Jinglun ,  GUDGER, Keith, H. ,  YU, Joe ,  SHARP, Steven, A.

IPC: H03K19/177

CPC classification number: H03K19/1737

Abstract: A circuit package (Fig. 1) including a plurality of macrocells (17) for connecting a logic circuit (13) of the package to a plurality of external contacts (15). At least one of the macrocells (Fig. 2) has an output driver (47) that is enabled or disabled by a control signal. This signal is generated by a logic gate (69) that logically combines an output enable signal (OE; 71) dedicated to that particular macrocell with a selected signal (73). One signal that may be selected is a regional output enable signal (ROE) that is supplied to several macrocells. Each macrocell also has a feedback multiplexer (77) selecting one signal to be sent to the logic circuit. Choices include a nonstored logic signal (85), a stored logic signal (83) from a register (25) in the macrocell, a signal (79) applied to the external contact (PIN N) associated with that macrocell, and a signal (81) applied to another contact (PIN N+1) associated with a different macrocell. A plurality of contacts are connected to feedback multiplexers (N-1, N, etc.) in different macrocells, and at least one contact connects in this manner to separate regions (I, I+1, etc.) of the logic circuit (Fig. 3). The flip-flop register (25) in the macrocell (Fig. 2) has a choice of data inputs selected by another multiplexer (35) from among at least one logic signal (37, 39) from the logic circuit and at least one signal (41) applied to an external contact (PIN N).