公开(公告)号：WO1993018586A1

公开(公告)日：1993-09-16

申请号：PCT/US1993000469

申请日：1993-01-19

Applicant: ATMEL CORPORATION

Inventor： ATMEL CORPORATION ,  GONGWER, Geoffrey, S. ,  TAM, Jinglun ,  GUDGER, Keith, H. ,  YU, Joe ,  SHARP, Steven, A.

IPC: H03K19/177

CPC classification number: H03K19/1737

Abstract: A circuit package (Fig. 1) including a plurality of macrocells (17) for connecting a logic circuit (13) of the package to a plurality of external contacts (15). At least one of the macrocells (Fig. 2) has an output driver (47) that is enabled or disabled by a control signal. This signal is generated by a logic gate (69) that logically combines an output enable signal (OE; 71) dedicated to that particular macrocell with a selected signal (73). One signal that may be selected is a regional output enable signal (ROE) that is supplied to several macrocells. Each macrocell also has a feedback multiplexer (77) selecting one signal to be sent to the logic circuit. Choices include a nonstored logic signal (85), a stored logic signal (83) from a register (25) in the macrocell, a signal (79) applied to the external contact (PIN N) associated with that macrocell, and a signal (81) applied to another contact (PIN N+1) associated with a different macrocell. A plurality of contacts are connected to feedback multiplexers (N-1, N, etc.) in different macrocells, and at least one contact connects in this manner to separate regions (I, I+1, etc.) of the logic circuit (Fig. 3). The flip-flop register (25) in the macrocell (Fig. 2) has a choice of data inputs selected by another multiplexer (35) from among at least one logic signal (37, 39) from the logic circuit and at least one signal (41) applied to an external contact (PIN N).

公开(公告)号：WO1995030952A1

公开(公告)日：1995-11-16

申请号：PCT/US1995005436

申请日：1995-05-02

Applicant: ATMEL CORPORATION

Inventor： ATMEL CORPORATION ,  KHONG, James, C., K. ,  MUELLER, Wendey, E. ,  YU, Joe ,  BERGER, Neal ,  GUDGER, Keith, H. ,  GONGWER, Geoffrey, S.

IPC: G06F07/38

CPC classification number: H03K19/1736 ,  H03K19/1737

Abstract: A programmable logic device having a plurality of logic cells (151-15N) arranged in groups defining separate logic regions (111-11N), both regional (191-19N) and multi-regional (13) bus lines, and a crosspoint switch matrix (37) which serves only to route signals from bus lines (391-39J and 401-40L) to inputs of the logic cells (311-31J) without logically combining two or more of the bus signals, i.e. without forming product terms. Rather, all logic is carried out by the logic cells (311-31J) themselves. In particular, the switch matrix (37) is constructed so that each bus line (391-39J and 401-40L) can connect to one or more logic cell inputs, but each logic cell input can meaningfully connect to only one bus line without shorting. In one embodiment, each logic cell (311-31J) feeds one logic signal back (411-41J) to a regional bus line (191) and can potentially feed back another logic signal through its region's universal select matrix (47) to a universal bus line (13). The select matrix (47) connects a subset of the region's potential feedback signals to the universal bus (13).

Abstract translation: 一种可编程逻辑器件，具有多个逻辑单元（151-15N），其以限定单独的逻辑区域（111-11N），区域（191-19N）和多区域（13）总线线路以及交叉点开关矩阵 （37），其仅用于将信号从总线（391-39J和401-40L）传送到逻辑单元（311-31J）的输入，而不逻辑地组合两个或更多个总线信号，即不形成乘积项。 相反，所有逻辑由逻辑单元（311-31J）本身执行。 特别地，开关矩阵（37）被构造成使得每个总线（391-39J和401-40L）可以连接到一个或多个逻辑单元输入，但是每个逻辑单元输入可以有意义地连接到仅一条总线而不短路 。 在一个实施例中，每个逻辑单元（311-31J）将一个逻辑信号（411-41J）馈送到区域总线（191），并且可以将另一个逻辑信号通过其区域的通用选择矩阵（47）反馈到通用 总线（13）。 选择矩阵（47）将该区域的潜在反馈信号的子集连接到通用总线（13）。