公开(公告)号：WO2022006379A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/040059

申请日：2021-07-01

Applicant: ATOMERA INCORPORATED

Inventor： WEEKS, Keith Doran ,  CODY, Nyles Wynn ,  HYTHA, Marek ,  MEARS, Robert J. ,  STEPHENSON, Robert John ,  TAKEUCHI, Hideki

IPC: H01L29/15 ,  H01L29/152 ,  H01L29/66477 ,  H01L29/7849

Abstract: A semiconductor device (120) may include a semiconductor layer (121) and a superlattice (125) adjacent the semiconductor layer. The superlattice may include stacked groups of layers (145a, 145b), with each group of layers comprising stacked base semiconductor monolayers (146a, 146b) defining a base semiconductor portion, and at least one non-semiconductor monolayer (150a, 150b) constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer (150a) in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer (150b) in a second group of layers of the superlattice may comprise carbon.

公开(公告)号：WO2023076228A1

公开(公告)日：2023-05-04

申请号：PCT/US2022/047676

申请日：2022-10-25

Applicant: ATOMERA INCORPORATED

Inventor： HYTHA, Marek ,  WEEKS, Keith Doran ,  CODY, Nyles Wynn

IPC: H01L21/3065 ,  H01L29/10 ,  H01L29/15

Abstract: A method for making a semiconductor device may include forming a superlattice above a semiconductor layer, the superlattice including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate adjacent the semiconductor layer, epitaxially growing an active semiconductor device layer above the semiconductor layer and accumulated non-semiconductor atoms after the selective etching, and forming at least one circuit in the epitaxially grown active semiconductor device layer.

公开(公告)号：WO2020092492A1

公开(公告)日：2020-05-07

申请号：PCT/US2019/058748

申请日：2019-10-30

Applicant: ATOMERA INCORPORATED

Inventor： WEEKS, Keith Doran ,  CODY, Nyles Wynn ,  HYTHA, Marek ,  MEARS, Robert J. ,  STEPHENSON, Robert John ,  HUTTER III, Louis Nicholas

IPC: H01L21/02 ,  H01L29/15

Abstract: A method for making a semiconductor device may include forming a superlattice layer and an adjacent semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include diffusing nitrogen into the superlattice layer.

公开(公告)号：WO2021173463A1

公开(公告)日：2021-09-02

申请号：PCT/US2021/018972

申请日：2021-02-22

Applicant: ATOMERA INCORPORATED

Inventor： WEEKS, Keith Doran ,  CODY, Nyles Wynn

IPC: H01L29/15

Abstract: A semiconductor device may include a semiconductor substrate (121), and a superlattice (125) on the semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers (146a-146e) defining a base semiconductor portion and at least one non-semiconductor monolayer (150a-150f) constrained within a crystal lattice of adjacent base semiconductor portions. A first at least one non-semiconductor monolayer (150a-150c) may be constrained within the crystal lattice of a first pair of adjacent base semiconductor portions and comprise a first non-semiconductor material, and a second at least one non- semiconductor monolayer (150d-150e) may be constrained within the crystal lattice of a second pair of adjacent base semiconductor portions and comprise a second non-semiconductor material different than the first non-semiconductor material.

公开(公告)号：WO2020046890A1

公开(公告)日：2020-03-05

申请号：PCT/US2019/048277

申请日：2019-08-27

Applicant: ATOMERA INCORPORATED

Inventor： WEEKS, Keith Doran ,  CODY, Nyles Wynn ,  HYTHA, Marek ,  MEARS, Robert J. ,  STEPHENSON, Robert John

IPC: H01L29/15 ,  H01L21/02 ,  H01L29/78

Abstract: A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

公开(公告)号：WO2023076229A1

公开(公告)日：2023-05-04

申请号：PCT/US2022/047678

申请日：2022-10-25

Applicant: ATOMERA INCORPORATED

Inventor： HYTHA, Marek ,  WEEKS, Keith Doran ,  CODY, Nyles Wynn

IPC: H01L21/3065 ,  H01L29/15 ,  H01L29/78

Abstract: A method for making a semiconductor device may include forming a superlattice above a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate and define an etch stop layer.

公开(公告)号：WO2022225901A1

公开(公告)日：2022-10-27

申请号：PCT/US2022/025307

申请日：2022-04-19

Applicant: ATOMERA INCORPORATED

Inventor： HYTHA, Marek ,  WEEKS, Keith Doran ,  CODY, Nyles Wynn ,  TAKEUCHI, Hideki

IPC: H01L21/02

Abstract: A semiconductor device may include a first single crystal silicon layer having a first percentage of silicon 28; a second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28; and a superlattice between the first and second single crystal silicon layers. The superlattice may include stacked groups of layers, with each group of layers including stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions.

公开(公告)号：WO2022251173A1

公开(公告)日：2022-12-01

申请号：PCT/US2022/030669

申请日：2022-05-24

Applicant: ATOMERA INCORPORATED

Inventor： HYTHA, Marek ,  CODY, Nyles Wynn ,  WEEKS, Keith Doran

IPC: H01L29/15 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

Abstract: A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may include an atomic percentage of 18O greater than 10 percent.

公开(公告)号：WO2022006396A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/040088

申请日：2021-07-01

Applicant: ATOMERA INCORPORATED

Inventor： WEEKS, Keith Doran ,  CODY, Nyles Wynn ,  HYTHA, Marek ,  MEARS, Robert J.

IPC: H01L29/15 ,  H01L21/02 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/3225 ,  H01L29/152

Abstract: A method for making a semiconductor device may include forming first and second superlattices adjacent a semiconductor layer. Each of the first and second superlattices may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The second superlattice may have a greater thermal stability with respect to non-semiconductor atoms therein than the first superlattice. The method may further include heating the first and second superlattices to cause non-semiconductor atoms from the first superlattice to migrate toward the at least one non-semiconductor monolayer of the second superlattice.

公开(公告)号：WO2021178367A1

公开(公告)日：2021-09-10

申请号：PCT/US2021/020404

申请日：2021-03-02

Applicant: ATOMERA INCORPORATED

Inventor： CODY, Nyles Wynn ,  WEEKS, Keith Doran ,  STEPHENSON, Robert John ,  BURTON, Richard ,  CHEN, Yi-Ann ,  CHOUTOV, Dmitri ,  TAKEUCHI, Hideki ,  YANG, Yung-Hsuan

IPC: H01L29/15 ,  H01L21/762 ,  H01L29/78

Abstract: A method for making a semiconductor device may include forming an isolation region adjacent an active region in a semiconductor substrate, and selectively etching the active region so that an upper surface of the active region is below an adjacent surface of the isolation region and defining a stepped edge therewith. The method may further include forming a superlattice overlying the active region. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.