公开(公告)号：WO2022006396A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/040088

申请日：2021-07-01

Applicant: ATOMERA INCORPORATED

Inventor： WEEKS, Keith Doran ,  CODY, Nyles Wynn ,  HYTHA, Marek ,  MEARS, Robert J.

IPC: H01L29/15 ,  H01L21/02 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/3225 ,  H01L29/152

Abstract: A method for making a semiconductor device may include forming first and second superlattices adjacent a semiconductor layer. Each of the first and second superlattices may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The second superlattice may have a greater thermal stability with respect to non-semiconductor atoms therein than the first superlattice. The method may further include heating the first and second superlattices to cause non-semiconductor atoms from the first superlattice to migrate toward the at least one non-semiconductor monolayer of the second superlattice.

公开(公告)号：WO2022240716A2

公开(公告)日：2022-11-17

申请号：PCT/US2022/028264

申请日：2022-05-09

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： CHAN, Philip ,  DENBAARS, Steven P. ,  NAKAMURA, Shuji

IPC: H01L21/205 ,  C30B25/10 ,  H01L21/02 ,  H01L33/04 ,  H01L33/12 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/7806 ,  H01L33/007 ,  H01S2301/173 ,  H01S5/0216 ,  H01S5/0217 ,  H01S5/04253 ,  H01S5/2068 ,  H01S5/22 ,  H01S5/3063 ,  H01S5/3213 ,  H01S5/34333

Abstract: A III-nitride based device is fabricated having an in-plane lattice constant or strain that is more than 30% biaxially relaxed, by creating a III-nitride based decomposition stop layer on or above a III-nitride based decomposition layer, wherein a temperature is increased to decompose the III-nitride based decomposition layer; and growing a III-nitride based device structure on or above the III-nitride based decomposition stop layer. The III-nitride based device structure includes at least one of an n-type layer, active layer, and p-type layer, and at least one of the n-type layer, active layer and p-type layer has an in-plane lattice constant or strain that is preferably more than 30% biaxially relaxed, more preferably 50% or more biaxially relaxed, and most preferably at least 70% biaxially relaxed.

公开(公告)号：WO2022182531A2

公开(公告)日：2022-09-01

申请号：PCT/US2022/016056

申请日：2022-02-11

Applicant: NORTHWESTERN UNIVERSITY

Inventor： RAZEGHI, Manijeh

IPC: C01G15/00 ,  H01L21/02 ,  H01L21/365 ,  H01L29/24 ,  H01L21/0242 ,  H01L21/02483 ,  H01L21/02507 ,  H01L21/02565 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262

Abstract: Methods of forming k-phase gallium oxide materials are provided, including highly conductive and highly phase stable such materials. In embodiments, the method comprises exposing a surface of a substrate positioned in a metalorganic chemical vapor deposition (MOCVD) reactor to a gallium (Ga) precursor vapor, an indium (In) precursor vapor, an oxygen (O) precursor vapor, and a silicon (Si) precursor vapor, under conditions to form a k-phase gallium oxide material on the surface of the substrate. The k-phase gallium oxide material comprises Ga, O, Si, and further comprises no more than 0.1 weight% In.

公开(公告)号：WO2021255426A1

公开(公告)日：2021-12-23

申请号：PCT/GB2021/051485

申请日：2021-06-15

Applicant: UNIVERSITY OF LANCASTER

Inventor： CARRINGTON, Peter ,  DELLI, Evangelia

IPC: H01L21/20 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549

Abstract: A semiconductor device comprises a substrate, one or more first III- semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.